NXP Semiconductors MK53DZ10 2024.06.02 MK53DZ10 Freescale Microcontroller CM4 r0p1 little 4 false 8 32 ADC0 Analog-to-Digital Converter ADC 0x0 0x0 0x70 registers n ADC0 57 CFG1 ADC configuration register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input clock select 0 2 read-write 00 Bus clock. #00 01 Bus clock divided by 2. #01 10 Alternate clock (ALTCLK). #10 11 Asynchronous clock (ADACK). #11 ADIV Clock divide select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-power configuration 7 1 read-write 0 Normal power configuration. #0 1 Low power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output. #10 11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output . #11 CFG2 Configuration register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous clock output enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output enabled regardless of the state of the ADC. #1 ADHSC High speed configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). #1 ADLSTS Long sample time select 0 2 read-write 00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 CLM0 ADC minus-side general calibration value register 0x6C 32 read-write n 0x0 0x0 CLM0 no description available 0 6 read-write CLM1 ADC minus-side general calibration value register 0x68 32 read-write n 0x0 0x0 CLM1 no description available 0 7 read-write CLM2 ADC minus-side general calibration value register 0x64 32 read-write n 0x0 0x0 CLM2 no description available 0 8 read-write CLM3 ADC minus-side general calibration value register 0x60 32 read-write n 0x0 0x0 CLM3 no description available 0 9 read-write CLM4 ADC minus-side general calibration value register 0x5C 32 read-write n 0x0 0x0 CLM4 no description available 0 10 read-write CLMD ADC minus-side general calibration value register 0x54 32 read-write n 0x0 0x0 CLMD no description available 0 6 read-write CLMS ADC minus-side general calibration value register 0x58 32 read-write n 0x0 0x0 CLMS no description available 0 6 read-write CLP0 ADC plus-side general calibration value register 0x4C 32 read-write n 0x0 0x0 CLP0 no description available 0 6 read-write CLP1 ADC plus-side general calibration value register 0x48 32 read-write n 0x0 0x0 CLP1 no description available 0 7 read-write CLP2 ADC plus-side general calibration value register 0x44 32 read-write n 0x0 0x0 CLP2 no description available 0 8 read-write CLP3 ADC plus-side general calibration value register 0x40 32 read-write n 0x0 0x0 CLP3 no description available 0 9 read-write CLP4 ADC plus-side general calibration value register 0x3C 32 read-write n 0x0 0x0 CLP4 no description available 0 10 read-write CLPD ADC plus-side general calibration value register 0x34 32 read-write n 0x0 0x0 CLPD no description available 0 6 read-write CLPS ADC plus-side general calibration value register 0x38 32 read-write n 0x0 0x0 CLPS no description available 0 6 read-write CV1 Compare value registers 0x30 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write CV2 Compare value registers 0x4C 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write MG ADC minus-side gain register 0x30 32 read-write n 0x0 0x0 MG Minus-side gain 0 16 read-write OFS ADC offset correction register 0x28 32 read-write n 0x0 0x0 OFS Offset error correction value 0 16 read-write PG ADC plus-side gain register 0x2C 32 read-write n 0x0 0x0 PG Plus-side gain 0 16 read-write PGA ADC PGA register 0x50 32 read-write n 0x0 0x0 PGAEN PGA enable 23 1 read-write 0 PGA disabled. #0 1 PGA enabled. #1 PGAG PGA gain setting 16 4 read-write 0000 1 #0000 0001 2 #0001 0010 4 #0010 0011 8 #0011 0100 16 #0100 0101 32 #0101 0110 64 #0110 PGALPb PGA low-power mode control 20 1 read-write 0 PGA runs in low power mode. #0 1 PGA runs in normal power mode. #1 RA ADC data result register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RB ADC data result register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only SC1A ADC status and control registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC1B ADC status and control registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC2 Status and control register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare function enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare function greater than enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers. #0 1 Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers. #1 ACREN Compare function range enable 3 1 read-write 0 Range function disabled. Only the compare value 1 register (CV1) is compared. #0 1 Range function enabled. Both compare value registers (CV1 and CV2) are compared. #1 ADACT Conversion active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion trigger select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags. #1 REFSEL Voltage reference selection 0 2 read-write 00 Default voltage reference pin pair (external pins VREFH and VREFL) #00 01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. #01 SC3 Status and control register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous conversion enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #1 AVGE Hardware average enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware average select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration failed flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 ADC1 Analog-to-Digital Converter ADC 0x0 0x0 0x70 registers n ADC1 58 CFG1 ADC configuration register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input clock select 0 2 read-write 00 Bus clock. #00 01 Bus clock divided by 2. #01 10 Alternate clock (ALTCLK). #10 11 Asynchronous clock (ADACK). #11 ADIV Clock divide select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-power configuration 7 1 read-write 0 Normal power configuration. #0 1 Low power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output. #10 11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output . #11 CFG2 Configuration register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous clock output enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output enabled regardless of the state of the ADC. #1 ADHSC High speed configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). #1 ADLSTS Long sample time select 0 2 read-write 00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 CLM0 ADC minus-side general calibration value register 0x6C 32 read-write n 0x0 0x0 CLM0 no description available 0 6 read-write CLM1 ADC minus-side general calibration value register 0x68 32 read-write n 0x0 0x0 CLM1 no description available 0 7 read-write CLM2 ADC minus-side general calibration value register 0x64 32 read-write n 0x0 0x0 CLM2 no description available 0 8 read-write CLM3 ADC minus-side general calibration value register 0x60 32 read-write n 0x0 0x0 CLM3 no description available 0 9 read-write CLM4 ADC minus-side general calibration value register 0x5C 32 read-write n 0x0 0x0 CLM4 no description available 0 10 read-write CLMD ADC minus-side general calibration value register 0x54 32 read-write n 0x0 0x0 CLMD no description available 0 6 read-write CLMS ADC minus-side general calibration value register 0x58 32 read-write n 0x0 0x0 CLMS no description available 0 6 read-write CLP0 ADC plus-side general calibration value register 0x4C 32 read-write n 0x0 0x0 CLP0 no description available 0 6 read-write CLP1 ADC plus-side general calibration value register 0x48 32 read-write n 0x0 0x0 CLP1 no description available 0 7 read-write CLP2 ADC plus-side general calibration value register 0x44 32 read-write n 0x0 0x0 CLP2 no description available 0 8 read-write CLP3 ADC plus-side general calibration value register 0x40 32 read-write n 0x0 0x0 CLP3 no description available 0 9 read-write CLP4 ADC plus-side general calibration value register 0x3C 32 read-write n 0x0 0x0 CLP4 no description available 0 10 read-write CLPD ADC plus-side general calibration value register 0x34 32 read-write n 0x0 0x0 CLPD no description available 0 6 read-write CLPS ADC plus-side general calibration value register 0x38 32 read-write n 0x0 0x0 CLPS no description available 0 6 read-write CV1 Compare value registers 0x30 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write CV2 Compare value registers 0x4C 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write MG ADC minus-side gain register 0x30 32 read-write n 0x0 0x0 MG Minus-side gain 0 16 read-write OFS ADC offset correction register 0x28 32 read-write n 0x0 0x0 OFS Offset error correction value 0 16 read-write PG ADC plus-side gain register 0x2C 32 read-write n 0x0 0x0 PG Plus-side gain 0 16 read-write PGA ADC PGA register 0x50 32 read-write n 0x0 0x0 PGAEN PGA enable 23 1 read-write 0 PGA disabled. #0 1 PGA enabled. #1 PGAG PGA gain setting 16 4 read-write 0000 1 #0000 0001 2 #0001 0010 4 #0010 0011 8 #0011 0100 16 #0100 0101 32 #0101 0110 64 #0110 PGALPb PGA low-power mode control 20 1 read-write 0 PGA runs in low power mode. #0 1 PGA runs in normal power mode. #1 RA ADC data result register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RB ADC data result register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only SC1A ADC status and control registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC1B ADC status and control registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC2 Status and control register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare function enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare function greater than enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers. #0 1 Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers. #1 ACREN Compare function range enable 3 1 read-write 0 Range function disabled. Only the compare value 1 register (CV1) is compared. #0 1 Range function enabled. Both compare value registers (CV1 and CV2) are compared. #1 ADACT Conversion active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion trigger select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags. #1 REFSEL Voltage reference selection 0 2 read-write 00 Default voltage reference pin pair (external pins VREFH and VREFL) #00 01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. #01 SC3 Status and control register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous conversion enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #1 AVGE Hardware average enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware average select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration failed flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 AIPS0 AIPS-Lite Bridge AIPS 0x0 0x0 0x70 registers n MPRA Master Privilege Register A 0x0 32 read-write n 0x0 0x0 MPL0 Master privilege level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL1 Master privilege level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL2 Master privilege level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL3 Master privilege level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL4 Master privilege level 12 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL5 Master privilege level 8 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTR0 Master trusted for read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR1 Master trusted for read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR2 Master trusted for read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR3 Master trusted for read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR4 Master trusted for read 14 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR5 Master trusted for read 10 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTW0 Master trusted for writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW1 Master trusted for writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW2 Master trusted for writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW3 Master trusted for writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW4 Master trusted for writes 13 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW5 Master trusted for writes 9 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRB Peripheral Access Control Register 0x24 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRC Peripheral Access Control Register 0x28 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRE Peripheral Access Control Register 0x40 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRF Peripheral Access Control Register 0x44 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRG Peripheral Access Control Register 0x48 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRI Peripheral Access Control Register 0x50 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRK Peripheral Access Control Register 0x58 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRM Peripheral Access Control Register 0x60 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRN Peripheral Access Control Register 0x64 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRO Peripheral Access Control Register 0x68 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 AIPS1 AIPS-Lite Bridge AIPS 0x0 0x0 0x70 registers n MPRA Master Privilege Register A 0x0 32 read-write n 0x0 0x0 MPL0 Master privilege level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL1 Master privilege level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL2 Master privilege level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL3 Master privilege level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL4 Master privilege level 12 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL5 Master privilege level 8 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTR0 Master trusted for read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR1 Master trusted for read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR2 Master trusted for read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR3 Master trusted for read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR4 Master trusted for read 14 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR5 Master trusted for read 10 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTW0 Master trusted for writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW1 Master trusted for writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW2 Master trusted for writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW3 Master trusted for writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW4 Master trusted for writes 13 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW5 Master trusted for writes 9 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRB Peripheral Access Control Register 0x24 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRC Peripheral Access Control Register 0x28 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRE Peripheral Access Control Register 0x40 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRF Peripheral Access Control Register 0x44 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRG Peripheral Access Control Register 0x48 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRI Peripheral Access Control Register 0x50 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRK Peripheral Access Control Register 0x58 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRM Peripheral Access Control Register 0x60 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRN Peripheral Access Control Register 0x64 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRO Peripheral Access Control Register 0x68 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write n 0x0 0x0 SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 AXBS Crossbar switch AXBS 0x0 0x0 0xD04 registers n CRS0 Control Register 0x20 32 read-write n 0x0 0x0 ARB Arbitration mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt low priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 PCTL Parking control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS1 Control Register 0x130 32 read-write n 0x0 0x0 ARB Arbitration mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt low priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 PCTL Parking control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS2 Control Register 0x340 32 read-write n 0x0 0x0 ARB Arbitration mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt low priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 PCTL Parking control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS3 Control Register 0x650 32 read-write n 0x0 0x0 ARB Arbitration mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt low priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 PCTL Parking control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS4 Control Register 0xA60 32 read-write n 0x0 0x0 ARB Arbitration mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt low priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 PCTL Parking control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 MGPCR0 Master General Purpose Control Register 0x1000 32 read-write n 0x0 0x0 AULB Arbitrates on undefined length bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR1 Master General Purpose Control Register 0x1900 32 read-write n 0x0 0x0 AULB Arbitrates on undefined length bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR2 Master General Purpose Control Register 0x2300 32 read-write n 0x0 0x0 AULB Arbitrates on undefined length bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR3 Master General Purpose Control Register 0x2E00 32 read-write n 0x0 0x0 AULB Arbitrates on undefined length bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR4 Master General Purpose Control Register 0x3A00 32 read-write n 0x0 0x0 AULB Arbitrates on undefined length bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR5 Master General Purpose Control Register 0x4700 32 read-write n 0x0 0x0 AULB Arbitrates on undefined length bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 PRS0 Priority Registers Slave 0x0 32 read-write n 0x0 0x0 M0 Master 0 priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS1 Priority Registers Slave 0x100 32 read-write n 0x0 0x0 M0 Master 0 priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS2 Priority Registers Slave 0x300 32 read-write n 0x0 0x0 M0 Master 0 priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS3 Priority Registers Slave 0x600 32 read-write n 0x0 0x0 M0 Master 0 priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS4 Priority Registers Slave 0xA00 32 read-write n 0x0 0x0 M0 Master 0 priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 CAU Memory Mapped Cryptographic Acceleration Unit (MMCAU) CAU 0x0 0x0 0xB6C registers n ADR_CA0 General Purpose Register 0 - Add to register command 0x8C8 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only ADR_CA1 General Purpose Register 1 - Add to register command 0x8CC 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only ADR_CA2 General Purpose Register 2 - Add to register command 0x8D0 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only ADR_CA3 General Purpose Register 3 - Add to register command 0x8D4 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only ADR_CA4 General Purpose Register 4 - Add to register command 0x8D8 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only ADR_CA5 General Purpose Register 5 - Add to register command 0x8DC 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only ADR_CA6 General Purpose Register 6 - Add to register command 0x8E0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only ADR_CA7 General Purpose Register 7 - Add to register command 0x8E4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only ADR_CA8 General Purpose Register 8 - Add to register command 0x8E8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only ADR_CAA Accumulator register - Add to register command 0x8C4 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only ADR_CASR Status register - Add Register command 0x8C0 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 AESC_CA0 General Purpose Register 0 - AES Column Operation command 0xB08 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only AESC_CA1 General Purpose Register 1 - AES Column Operation command 0xB0C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only AESC_CA2 General Purpose Register 2 - AES Column Operation command 0xB10 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only AESC_CA3 General Purpose Register 3 - AES Column Operation command 0xB14 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only AESC_CA4 General Purpose Register 4 - AES Column Operation command 0xB18 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only AESC_CA5 General Purpose Register 5 - AES Column Operation command 0xB1C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only AESC_CA6 General Purpose Register 6 - AES Column Operation command 0xB20 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only AESC_CA7 General Purpose Register 7 - AES Column Operation command 0xB24 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only AESC_CA8 General Purpose Register 8 - AES Column Operation command 0xB28 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only AESC_CAA Accumulator register - AES Column Operation command 0xB04 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only AESC_CASR Status register - AES Column Operation command 0xB00 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 AESIC_CA0 General Purpose Register 0 - AES Inverse Column Operation command 0xB48 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only AESIC_CA1 General Purpose Register 1 - AES Inverse Column Operation command 0xB4C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only AESIC_CA2 General Purpose Register 2 - AES Inverse Column Operation command 0xB50 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only AESIC_CA3 General Purpose Register 3 - AES Inverse Column Operation command 0xB54 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only AESIC_CA4 General Purpose Register 4 - AES Inverse Column Operation command 0xB58 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only AESIC_CA5 General Purpose Register 5 - AES Inverse Column Operation command 0xB5C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only AESIC_CA6 General Purpose Register 6 - AES Inverse Column Operation command 0xB60 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only AESIC_CA7 General Purpose Register 7 - AES Inverse Column Operation command 0xB64 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only AESIC_CA8 General Purpose Register 8 - AES Inverse Column Operation command 0xB68 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only AESIC_CAA Accumulator register - AES Inverse Column Operation command 0xB44 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only AESIC_CASR Status register - AES Inverse Column Operation command 0xB40 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 DIRECT0 Direct access register 0 0x0 32 write-only n 0x0 0x0 CAU_DIRECT0 Direct register 0 0 32 write-only DIRECT1 Direct access register 1 0x4 32 write-only n 0x0 0x0 CAU_DIRECT1 Direct register 1 0 32 write-only DIRECT10 Direct access register 10 0x28 32 write-only n 0x0 0x0 CAU_DIRECT10 Direct register 10 0 32 write-only DIRECT11 Direct access register 11 0x2C 32 write-only n 0x0 0x0 CAU_DIRECT11 Direct register 11 0 32 write-only DIRECT12 Direct access register 12 0x30 32 write-only n 0x0 0x0 CAU_DIRECT12 Direct register 12 0 32 write-only DIRECT13 Direct access register 13 0x34 32 write-only n 0x0 0x0 CAU_DIRECT13 Direct register 13 0 32 write-only DIRECT14 Direct access register 14 0x38 32 write-only n 0x0 0x0 CAU_DIRECT14 Direct register 14 0 32 write-only DIRECT15 Direct access register 15 0x3C 32 write-only n 0x0 0x0 CAU_DIRECT15 Direct register 15 0 32 write-only DIRECT2 Direct access register 2 0x8 32 write-only n 0x0 0x0 CAU_DIRECT2 Direct register 2 0 32 write-only DIRECT3 Direct access register 3 0xC 32 write-only n 0x0 0x0 CAU_DIRECT3 Direct register 3 0 32 write-only DIRECT4 Direct access register 4 0x10 32 write-only n 0x0 0x0 CAU_DIRECT4 Direct register 4 0 32 write-only DIRECT5 Direct access register 5 0x14 32 write-only n 0x0 0x0 CAU_DIRECT5 Direct register 5 0 32 write-only DIRECT6 Direct access register 6 0x18 32 write-only n 0x0 0x0 CAU_DIRECT6 Direct register 6 0 32 write-only DIRECT7 Direct access register 7 0x1C 32 write-only n 0x0 0x0 CAU_DIRECT7 Direct register 7 0 32 write-only DIRECT8 Direct access register 8 0x20 32 write-only n 0x0 0x0 CAU_DIRECT8 Direct register 8 0 32 write-only DIRECT9 Direct access register 9 0x24 32 write-only n 0x0 0x0 CAU_DIRECT9 Direct register 9 0 32 write-only LDR_CA0 General Purpose Register 0 - Load Register command 0x848 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only LDR_CA1 General Purpose Register 1 - Load Register command 0x84C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only LDR_CA2 General Purpose Register 2 - Load Register command 0x850 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only LDR_CA3 General Purpose Register 3 - Load Register command 0x854 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only LDR_CA4 General Purpose Register 4 - Load Register command 0x858 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only LDR_CA5 General Purpose Register 5 - Load Register command 0x85C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only LDR_CA6 General Purpose Register 6 - Load Register command 0x860 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only LDR_CA7 General Purpose Register 7 - Load Register command 0x864 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only LDR_CA8 General Purpose Register 8 - Load Register command 0x868 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only LDR_CAA Accumulator register - Load Register command 0x844 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only LDR_CASR Status register - Load Register command 0x840 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 RADR_CA0 General Purpose Register 0 - Reverse and Add to Register command 0x908 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only RADR_CA1 General Purpose Register 1 - Reverse and Add to Register command 0x90C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only RADR_CA2 General Purpose Register 2 - Reverse and Add to Register command 0x910 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only RADR_CA3 General Purpose Register 3 - Reverse and Add to Register command 0x914 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only RADR_CA4 General Purpose Register 4 - Reverse and Add to Register command 0x918 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only RADR_CA5 General Purpose Register 5 - Reverse and Add to Register command 0x91C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only RADR_CA6 General Purpose Register 6 - Reverse and Add to Register command 0x920 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only RADR_CA7 General Purpose Register 7 - Reverse and Add to Register command 0x924 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only RADR_CA8 General Purpose Register 8 - Reverse and Add to Register command 0x928 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only RADR_CAA Accumulator register - Reverse and Add to Register command 0x904 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only RADR_CASR Status register - Reverse and Add to Register command 0x900 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 ROTL_CA0 General Purpose Register 0 - Rotate Left command 0x9C8 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only ROTL_CA1 General Purpose Register 1 - Rotate Left command 0x9CC 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only ROTL_CA2 General Purpose Register 2 - Rotate Left command 0x9D0 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only ROTL_CA3 General Purpose Register 3 - Rotate Left command 0x9D4 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only ROTL_CA4 General Purpose Register 4 - Rotate Left command 0x9D8 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only ROTL_CA5 General Purpose Register 5 - Rotate Left command 0x9DC 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only ROTL_CA6 General Purpose Register 6 - Rotate Left command 0x9E0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only ROTL_CA7 General Purpose Register 7 - Rotate Left command 0x9E4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only ROTL_CA8 General Purpose Register 8 - Rotate Left command 0x9E8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only ROTL_CAA Accumulator register - Rotate Left command 0x9C4 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only ROTL_CASR Status register - Rotate Left command 0x9C0 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 STR_CA0 General Purpose Register 0 - Store Register command 0x888 32 read-only n 0x0 0x0 CA0 CA0 0 32 read-only STR_CA1 General Purpose Register 1 - Store Register command 0x88C 32 read-only n 0x0 0x0 CA1 CA1 0 32 read-only STR_CA2 General Purpose Register 2 - Store Register command 0x890 32 read-only n 0x0 0x0 CA2 CA2 0 32 read-only STR_CA3 General Purpose Register 3 - Store Register command 0x894 32 read-only n 0x0 0x0 CA3 CA3 0 32 read-only STR_CA4 General Purpose Register 4 - Store Register command 0x898 32 read-only n 0x0 0x0 CA4 CA4 0 32 read-only STR_CA5 General Purpose Register 5 - Store Register command 0x89C 32 read-only n 0x0 0x0 CA5 CA5 0 32 read-only STR_CA6 General Purpose Register 6 - Store Register command 0x8A0 32 read-only n 0x0 0x0 CA6 CA6 0 32 read-only STR_CA7 General Purpose Register 7 - Store Register command 0x8A4 32 read-only n 0x0 0x0 CA7 CA7 0 32 read-only STR_CA8 General Purpose Register 8 - Store Register command 0x8A8 32 read-only n 0x0 0x0 CA8 CA8 0 32 read-only STR_CAA Accumulator register - Store Register command 0x884 32 read-only n 0x0 0x0 ACC ACC 0 32 read-only STR_CASR Status register - Store Register command 0x880 32 read-only n 0x0 0x0 DPE no description available 1 1 read-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 read-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 read-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 XOR_CA0 General Purpose Register 0 - Exclusive Or command 0x988 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only XOR_CA1 General Purpose Register 1 - Exclusive Or command 0x98C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only XOR_CA2 General Purpose Register 2 - Exclusive Or command 0x990 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only XOR_CA3 General Purpose Register 3 - Exclusive Or command 0x994 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only XOR_CA4 General Purpose Register 4 - Exclusive Or command 0x998 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only XOR_CA5 General Purpose Register 5 - Exclusive Or command 0x99C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only XOR_CA6 General Purpose Register 6 - Exclusive Or command 0x9A0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only XOR_CA7 General Purpose Register 7 - Exclusive Or command 0x9A4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only XOR_CA8 General Purpose Register 8 - Exclusive Or command 0x9A8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only XOR_CAA Accumulator register - Exclusive Or command 0x984 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only XOR_CASR Status register - Exclusive Or command 0x980 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP0 59 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MEN MMUX Enable 6 1 read-write 0 MMUX is disabled. #0 1 MMUX is enabled. #1 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PEN PMUX Enable 7 1 read-write 0 PMUX is disabled. #0 1 PMUX is enabled. #1 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SMELB Stop Mode Edge/Level Interrupt Control 5 1 read-write 0 CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be asserted when COUT is low. #0 1 CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF. #1 CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP1 60 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MEN MMUX Enable 6 1 read-write 0 MMUX is disabled. #0 1 MMUX is enabled. #1 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PEN PMUX Enable 7 1 read-write 0 PMUX is disabled. #0 1 PMUX is enabled. #1 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SMELB Stop Mode Edge/Level Interrupt Control 5 1 read-write 0 CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be asserted when COUT is low. #0 1 CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF. #1 CMP2 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP2 61 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MEN MMUX Enable 6 1 read-write 0 MMUX is disabled. #0 1 MMUX is enabled. #1 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PEN PMUX Enable 7 1 read-write 0 PMUX is disabled. #0 1 PMUX is enabled. #1 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SMELB Stop Mode Edge/Level Interrupt Control 5 1 read-write 0 CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be asserted when COUT is low. #0 1 CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF. #1 CMT Carrier Modulator Transmitter CMT 0x0 0x0 0xC registers n CMT 65 CGH1 CMT Carrier Generator High Data Register 1 0x0 8 read-write n 0x0 0x0 PH Primary Carrier High Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write n 0x0 0x0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write n 0x0 0x0 PL Primary Carrier Low Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write n 0x0 0x0 SL Secondary Carrier Low Time Data Value 0 8 read-write CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write n 0x0 0x0 MB no description available 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write n 0x0 0x0 MB no description available 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write n 0x0 0x0 SB no description available 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write n 0x0 0x0 SB no description available 0 8 read-write DMA CMT Direct Memory Access 0xB 8 read-write n 0x0 0x0 DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled #0 1 DMA transfer request and done are enabled #1 MSC CMT Modulator Status and Control Register 0x5 8 read-write n 0x0 0x0 BASE Baseband Enable 3 1 read-write 0 Baseband mode disabled #0 1 Baseband mode enabled #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 No end of modulation cycle occurrence since flag last cleared #0 1 End of modulator cycle has occurred #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt disabled #0 1 CPU interrupt enabled #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space disabled #0 1 Extended space enabled #1 FSK FSK Mode Select 2 1 read-write 0 CMT operates in Time or Baseband mode #0 1 CMT operates in FSK mode #1 MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 OC CMT Output Control Register 0x4 8 read-write n 0x0 0x0 CMTPOL CMT Output Polarity 6 1 read-write 0 CMT_IRO signal is active low #0 1 CMT_IRO signal is active high #1 IROL IRO Latch Control 7 1 read-write IROPEN IRO Pin Enable 5 1 read-write 0 CMT_IRO signal disabled #0 1 CMT_IRO signal enabled as output #1 PPS CMT Primary Prescaler Register 0xA 8 read-write n 0x0 0x0 PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus Clock * 1 #0000 0001 Bus Clock * 2 #0001 0010 Bus Clock * 3 #0010 0011 Bus Clock * 4 #0011 0100 Bus Clock * 5 #0100 0101 Bus Clock * 6 #0101 0110 Bus Clock * 7 #0110 0111 Bus Clock * 8 #0111 1000 Bus Clock * 9 #1000 1001 Bus Clock * 10 #1001 1010 Bus Clock * 11 #1010 1011 Bus Clock * 12 #1011 1100 Bus Clock * 13 #1100 1101 Bus Clock * 14 #1101 1110 Bus Clock * 15 #1110 1111 Bus Clock * 16 #1111 CRC Cyclic Redundancy Check CRC 0x0 0x0 0xC registers n CRC CRC Data Register CRC 0x0 32 read-write n 0x0 0x0 HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write CRCH CRC_CRCH register. CRC 0x2 16 read-write n 0x0 0x0 CRCH CRCH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write CRCHL CRC_CRCHL register. CRC 0x2 8 read-write n 0x0 0x0 CRCHL CRCHL stores the third 8 bits of the 32 bit CRC 0 8 read-write CRCHU CRC_CRCHU register. 0x3 8 read-write n 0x0 0x0 CRCHU CRCHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CRCL CRC_CRCL register. CRC 0x0 16 read-write n 0x0 0x0 CRCL CRCL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write CRCLL CRC_CRCLL register. CRC 0x0 8 read-write n 0x0 0x0 CRCLL CRCLL stores the first 8 bits of the 32 bit CRC 0 8 read-write CRCLU CRC_CRCLU register. 0x1 8 read-write n 0x0 0x0 CRCLU CRCLL stores the second 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control Register 0x8 32 read-write n 0x0 0x0 FXOR Complement Read of CRC data register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC data register. #1 TCRC no description available 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT Type of Transpose for Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR Type of Transpose for Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS Write CRC data register as seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 CTRLHU CRC_CTRLHU register. 0xB 8 read-write n 0x0 0x0 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 GPOLY CRC Polynomial Register CRC 0x4 32 read-write n 0x0 0x0 HIGH High polynominal half-word 16 16 read-write LOW Low polynominal half-word 0 16 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write n 0x0 0x0 GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write n 0x0 0x0 GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write n 0x0 0x0 GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write n 0x0 0x0 GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write n 0x0 0x0 GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write n 0x0 0x0 GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write DAC0 12-Bit Digital-to-Analog Converter DAC 0x0 0x0 0x24 registers n DAC0 81 C0 DAC Control Register 0x21 8 read-write n 0x0 0x0 DACBBIEN DAC buffer read pointer bottom flag interrupt enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC buffer read pointer top flag interrupt enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC buffer watermark interrupt enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 DACEN DAC enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selets DACREF_1 as the reference voltage. #0 1 The DAC selets DACREF_2 as the reference voltage. #1 DACSWTRG DAC software trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC trigger select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 LPEN DAC low power control 3 1 read-write 0 high power mode. #0 1 low power mode. #1 C1 DAC Control Register 1 0x22 8 read-write n 0x0 0x0 DACBFEN DAC buffer enable 0 1 read-write 0 Buffer read pointer disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC buffer work mode select 1 2 read-write 00 Normal Mode #00 01 Swing Mode #01 10 One-Time Scan Mode #10 DACBFWM DAC buffer watermark select 3 2 read-write 00 1 word #00 01 2 words #01 10 3 words #10 11 4 words #11 DMAEN DMA enable select 7 1 read-write 0 DMA disabled. #0 1 DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write n 0x0 0x0 DACBFRP DAC buffer read pointer 4 4 read-write DACBFUP DAC buffer upper limit 0 4 read-write DAT0H DAC Data High Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT0L DAC Data Low Register 0x0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT10H DAC Data High Register 0x7A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT10L DAC Data Low Register 0x6E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT11H DAC Data High Register 0x91 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT11L DAC Data Low Register 0x84 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT12H DAC Data High Register 0xAA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT12L DAC Data Low Register 0x9C 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT13H DAC Data High Register 0xC5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT13L DAC Data Low Register 0xB6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT14H DAC Data High Register 0xE2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT14L DAC Data Low Register 0xD2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT15H DAC Data High Register 0x101 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT15L DAC Data Low Register 0xF0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT1H DAC Data High Register 0x5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT1L DAC Data Low Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT2H DAC Data High Register 0xA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT2L DAC Data Low Register 0x6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT3H DAC Data High Register 0x11 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT3L DAC Data Low Register 0xC 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT4H DAC Data High Register 0x1A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT4L DAC Data Low Register 0x14 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT5H DAC Data High Register 0x25 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT5L DAC Data Low Register 0x1E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT6H DAC Data High Register 0x32 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT6L DAC Data Low Register 0x2A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT7H DAC Data High Register 0x41 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT7L DAC Data Low Register 0x38 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT8H DAC Data High Register 0x52 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT8L DAC Data Low Register 0x48 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT9H DAC Data High Register 0x65 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT9L DAC Data Low Register 0x5A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write SR DAC Status Register 0x20 8 read-write n 0x0 0x0 DACBFRPBF DAC buffer read pointer bottom position flag 0 1 read-write 0 The DAC buffer read pointer is not equal to the DACBFUP. #0 1 The DAC buffer read pointer is equal to the DACBFUP. #1 DACBFRPTF DAC buffer read pointer top position flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC buffer watermark flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 DAC1 12-Bit Digital-to-Analog Converter DAC 0x0 0x0 0x24 registers n DAC1 82 C0 DAC Control Register 0x21 8 read-write n 0x0 0x0 DACBBIEN DAC buffer read pointer bottom flag interrupt enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC buffer read pointer top flag interrupt enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC buffer watermark interrupt enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 DACEN DAC enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selets DACREF_1 as the reference voltage. #0 1 The DAC selets DACREF_2 as the reference voltage. #1 DACSWTRG DAC software trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC trigger select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 LPEN DAC low power control 3 1 read-write 0 high power mode. #0 1 low power mode. #1 C1 DAC Control Register 1 0x22 8 read-write n 0x0 0x0 DACBFEN DAC buffer enable 0 1 read-write 0 Buffer read pointer disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC buffer work mode select 1 2 read-write 00 Normal Mode #00 01 Swing Mode #01 10 One-Time Scan Mode #10 DACBFWM DAC buffer watermark select 3 2 read-write 00 1 word #00 01 2 words #01 10 3 words #10 11 4 words #11 DMAEN DMA enable select 7 1 read-write 0 DMA disabled. #0 1 DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write n 0x0 0x0 DACBFRP DAC buffer read pointer 4 4 read-write DACBFUP DAC buffer upper limit 0 4 read-write DAT0H DAC Data High Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT0L DAC Data Low Register 0x0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT10H DAC Data High Register 0x7A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT10L DAC Data Low Register 0x6E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT11H DAC Data High Register 0x91 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT11L DAC Data Low Register 0x84 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT12H DAC Data High Register 0xAA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT12L DAC Data Low Register 0x9C 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT13H DAC Data High Register 0xC5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT13L DAC Data Low Register 0xB6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT14H DAC Data High Register 0xE2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT14L DAC Data Low Register 0xD2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT15H DAC Data High Register 0x101 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT15L DAC Data Low Register 0xF0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT1H DAC Data High Register 0x5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT1L DAC Data Low Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT2H DAC Data High Register 0xA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT2L DAC Data Low Register 0x6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT3H DAC Data High Register 0x11 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT3L DAC Data Low Register 0xC 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT4H DAC Data High Register 0x1A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT4L DAC Data Low Register 0x14 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT5H DAC Data High Register 0x25 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT5L DAC Data Low Register 0x1E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT6H DAC Data High Register 0x32 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT6L DAC Data Low Register 0x2A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT7H DAC Data High Register 0x41 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT7L DAC Data Low Register 0x38 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT8H DAC Data High Register 0x52 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT8L DAC Data Low Register 0x48 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT9H DAC Data High Register 0x65 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write DAT9L DAC Data Low Register 0x5A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write SR DAC Status Register 0x20 8 read-write n 0x0 0x0 DACBFRPBF DAC buffer read pointer bottom position flag 0 1 read-write 0 The DAC buffer read pointer is not equal to the DACBFUP. #0 1 The DAC buffer read pointer is equal to the DACBFUP. #1 DACBFRPTF DAC buffer read pointer top position flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC buffer watermark flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 DMA Enhanced direct memory access controller DMA 0x0 0x0 0x1200 registers n DMA0 0 DMA1 1 DMA2 2 DMA3 3 DMA4 4 DMA5 5 DMA6 6 DMA7 7 DMA8 8 DMA9 9 DMA10 10 DMA11 11 DMA12 12 DMA13 13 DMA14 14 DMA15 15 DMA_Error 16 CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 CDNE Clear DONE Bit 0 4 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 CEEI Clear Enable Error Interrupt 0 4 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 CERQ Clear Enable Request 0 4 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 CERR Clear Error Indicator 0 4 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 CINT Clear Interrupt Request 0 4 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CR Control Register 0x0 32 read-write n 0x0 0x0 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. #1 EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection. #0 1 Round robin arbitration is used for channel selection. #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 DCHPRI0 Channel n Priority Register 0x506 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI1 Channel n Priority Register 0x403 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI10 Channel n Priority Register 0xB2D 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI11 Channel n Priority Register 0xA24 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI12 Channel n Priority Register 0x1178 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI13 Channel n Priority Register 0x1069 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI14 Channel n Priority Register 0xF5B 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI15 Channel n Priority Register 0xE4E 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI2 Channel n Priority Register 0x301 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI3 Channel n Priority Register 0x200 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI4 Channel n Priority Register 0x91C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI5 Channel n Priority Register 0x815 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI6 Channel n Priority Register 0x70F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI7 Channel n Priority Register 0x60A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI8 Channel n Priority Register 0xD42 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 DCHPRI9 Channel n Priority Register 0xC37 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI14 Enable Error Interrupt 14 14 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI15 Enable Error Interrupt 15 15 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ14 Enable DMA Request 14 14 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ15 Enable DMA Request 15 15 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR14 Error In Channel 14 14 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR15 Error In Channel 15 15 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 ECX Transfer Cancelled 16 1 read-only 0 No cancelled transfers #0 1 The last recorded entry was a cancelled transfer by the error cancel transfer input #1 ERRCHN Error Channel Number or Cancelled Channel Number 8 4 read-only NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 VLD no description available 31 1 read-only 0 No ERR bits are set #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared #1 HRS Hardware Request Status Register 0x34 32 read-write n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS14 Hardware Request Status Channel 14 14 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS15 Hardware Request Status Channel 15 15 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT14 Interrupt Request 14 14 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT15 Interrupt Request 15 15 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 SEEI Set Enable Error Interrupt 0 4 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 SERQ Set enable request 0 4 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 SSRT Set START Bit 0 4 write-only TCD0_ATTR TCD Transfer Attributes 0x200C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD0_CSR TCD Control and Status 0x2038 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD0_DADDR TCD Destination Address 0x2020 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x2030 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x2028 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x2010 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SADDR TCD Source Address 0x2000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x2018 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x2008 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0xC728 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xC848 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xC848 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xC7E8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xC7E8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD10_CSR TCD Control and Status 0xC830 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD10_DADDR TCD Destination Address 0xC7A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xC800 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0xC7D0 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xC740 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xC740 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xC740 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD10_SADDR TCD Source Address 0xC6E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD10_SLAST TCD Last Source Address Adjustment 0xC770 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0xC710 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0xD88E 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xD9C6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xD9C6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xD95E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xD95E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD11_CSR TCD Control and Status 0xD9AC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD11_DADDR TCD Destination Address 0xD910 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xD978 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0xD944 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xD8A8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xD8A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xD8A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD11_SADDR TCD Source Address 0xD840 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD11_SLAST TCD Last Source Address Adjustment 0xD8DC 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0xD874 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0xEA14 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xEB64 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xEB64 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xEAF4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xEAF4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD12_CSR TCD Control and Status 0xEB48 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD12_DADDR TCD Destination Address 0xEAA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xEB10 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0xEAD8 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xEA30 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xEA30 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xEA30 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD12_SADDR TCD Source Address 0xE9C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD12_SLAST TCD Last Source Address Adjustment 0xEA68 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0xE9F8 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0xFBBA 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xFD22 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xFD22 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xFCAA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xFCAA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD13_CSR TCD Control and Status 0xFD04 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD13_DADDR TCD Destination Address 0xFC50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xFCC8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0xFC8C 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xFBD8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xFBD8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xFBD8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD13_SADDR TCD Source Address 0xFB60 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD13_SLAST TCD Last Source Address Adjustment 0xFC14 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0xFB9C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x10D80 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x10F00 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x10F00 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x10E80 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x10E80 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD14_CSR TCD Control and Status 0x10EE0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD14_DADDR TCD Destination Address 0x10E20 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10EA0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x10E60 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x10DA0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x10DA0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x10DA0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD14_SADDR TCD Source Address 0x10D20 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD14_SLAST TCD Last Source Address Adjustment 0x10DE0 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x10D60 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11F66 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x120FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x120FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x12076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x12076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD15_CSR TCD Control and Status 0x120DC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD15_DADDR TCD Destination Address 0x12010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x12098 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x12054 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x11F88 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x11F88 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x11F88 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD15_SADDR TCD Source Address 0x11F00 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD15_SLAST TCD Last Source Address Adjustment 0x11FCC 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11F44 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x3032 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD1_CSR TCD Control and Status 0x3074 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD1_DADDR TCD Destination Address 0x3050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x3068 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x305C 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x3038 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SADDR TCD Source Address 0x3020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x3044 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x302C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x4078 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD2_CSR TCD Control and Status 0x40D0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD2_DADDR TCD Destination Address 0x40A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x40C0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x40B0 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x4080 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SADDR TCD Source Address 0x4060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x4090 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x4070 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x50DE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD3_CSR TCD Control and Status 0x514C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD3_DADDR TCD Destination Address 0x5110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x5138 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x5124 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x50E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SADDR TCD Source Address 0x50C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x50FC 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x50D4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x6164 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD4_CSR TCD Control and Status 0x61E8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD4_DADDR TCD Destination Address 0x61A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x61D0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x61B8 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x6170 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_SADDR TCD Source Address 0x6140 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD4_SLAST TCD Last Source Address Adjustment 0x6188 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x6158 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x720A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD5_CSR TCD Control and Status 0x72A4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD5_DADDR TCD Destination Address 0x7250 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x7288 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x726C 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x7218 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_SADDR TCD Source Address 0x71E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD5_SLAST TCD Last Source Address Adjustment 0x7234 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x71FC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x82D0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD6_CSR TCD Control and Status 0x8380 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD6_DADDR TCD Destination Address 0x8320 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x8360 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x8340 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x82E0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_SADDR TCD Source Address 0x82A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD6_SLAST TCD Last Source Address Adjustment 0x8300 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x82C0 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x93B6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD7_CSR TCD Control and Status 0x947C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD7_DADDR TCD Destination Address 0x9410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x9458 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x9434 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x93C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_SADDR TCD Source Address 0x9380 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD7_SLAST TCD Last Source Address Adjustment 0x93EC 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x93A4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0xA4BC 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xA5AC 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xA5AC 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xA55C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xA55C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD8_CSR TCD Control and Status 0xA598 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD8_DADDR TCD Destination Address 0xA520 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xA570 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0xA548 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xA4D0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xA4D0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xA4D0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD8_SADDR TCD Source Address 0xA480 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD8_SLAST TCD Last Source Address Adjustment 0xA4F8 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0xA4A8 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0xB5E2 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo. 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xB6EA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xB6EA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xB692 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xB692 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 4 read-write TCD9_CSR TCD Control and Status 0xB6D4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 4 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD9_DADDR TCD Destination Address 0xB650 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xB6A8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0xB67C 16 read-write n 0x0 0x0 DOFF Destination Address Signed offset 0 16 read-write TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xB5F8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xB5F8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xB5F8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD9_SADDR TCD Source Address 0xB5A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD9_SLAST TCD Last Source Address Adjustment 0xB624 32 read-write n 0x0 0x0 SLAST Last source Address Adjustment 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0xB5CC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write DMAMUX DMA channel multiplexor DMAMUX 0x0 0x0 0x10 registers n CHCFG0 Channel Configuration Register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG1 Channel Configuration Register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG10 Channel Configuration Register 0x37 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG11 Channel Configuration Register 0x42 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG12 Channel Configuration Register 0x4E 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG13 Channel Configuration Register 0x5B 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG14 Channel Configuration Register 0x69 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG15 Channel Configuration Register 0x78 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG2 Channel Configuration Register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG3 Channel Configuration Register 0x6 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG4 Channel Configuration Register 0xA 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG5 Channel Configuration Register 0xF 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG6 Channel Configuration Register 0x15 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG7 Channel Configuration Register 0x1C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG8 Channel Configuration Register 0x24 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG9 Channel Configuration Register 0x2D 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 ENET Ethernet MAC-NET Core ENET 0x0 0x4 0x624 registers n ENET_1588_Timer 75 ENET_Transmit 76 ENET_Receive 77 ENET_Error 78 ATCOR Timer Correction Register 0x410 32 read-write n 0x0 0x0 COR Correction counter wrap-around value 0 31 read-write ATCR Timer Control Register 0x400 32 read-write n 0x0 0x0 CAPTURE Capture timer value 11 1 read-write 0 No effect. #0 1 The current time is captured and can be read from the ATVR register. #1 EN Enable timer 0 1 read-write 0 The timer stops at the current value. #0 1 The timer starts incrementing. #1 OFFEN Enable one-shot offset event 2 1 read-write 0 Disable. #0 1 The timer can be reset to zero when the given offset time is reached (offset event). The bit is cleared when the offset event is reached, so no further event occurs until the bit is set again. Set the timer offset value before setting this bit. #1 OFFRST Reset timer on offset event 3 1 read-write 0 The timer is not affected and no action occurs (besides clearing OFFEN) when the offset is reached. #0 1 If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. #1 PEREN Enable periodical event 4 1 read-write 0 Disable. #0 1 A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. Set the timer period value before setting this bit. Not all devices contain the event signal output. See the Chip Configuration details. #1 PINPER no description available 7 1 read-write 0 Disable. #0 1 Enable. #1 RESTART Reset timer 9 1 read-write SLAVE Enable timer slave mode 13 1 read-write 0 The timer is active and all configuration bits in this register are relevant. #0 1 The internal timer is disabled and the externally provided timer value is used. All other bits, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. #1 ATINC Time-Stamping Clock Period Register 0x414 32 read-write n 0x0 0x0 INC Clock period of the timestamping clock (ts_clk) in nanoseconds 0 7 read-write INC_CORR Correction increment value 8 7 read-write ATOFF Timer Offset Register 0x408 32 read-write n 0x0 0x0 OFFSET no description available 0 32 read-write ATPER Timer Period Register 0x40C 32 read-write n 0x0 0x0 PERIOD no description available 0 32 read-write ATSTMP Timestamp of Last Transmitted Frame 0x418 32 read-write n 0x0 0x0 TIMESTAMP no description available 0 32 read-write ATVR Timer Value Register 0x404 32 read-write n 0x0 0x0 ATIME no description available 0 32 read-write ECR Ethernet Control Register 0x24 32 read-write n 0x0 0x0 DBGEN Debug enable 6 1 read-write 0 MAC continues operation in debug mode. #0 1 MAC enters hardware freeze mode when the processor is in debug mode. #1 EN1588 EN1588 enable 4 1 read-write 0 Legacy FEC buffer descriptors and functions enabled. #0 1 Enhanced frame time-stamping functions enabled. #1 ETHEREN Ethernet enable 1 1 read-write 0 Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. #0 1 MAC is enabled, and reception and transmission are possible. #1 MAGICEN Magic packet detection enable 2 1 read-write 0 Magic detection logic disabled #0 1 The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. #1 RESET Ethernet MAC reset 0 1 read-write SLEEP Sleep mode enable 3 1 read-write 0 Normal operating mode. #0 1 Sleep mode. #1 STOPEN STOPEN Signal Control 7 1 read-write EIMR Interrupt Mask Register 0x8 32 read-write n 0x0 0x0 BABR BABR interrupt mask 30 1 read-write 0 The corresponding interrupt source is masked. #0 1 The corresponding interrupt source is not masked. #1 BABT BABT interrupt mask 29 1 read-write 0 The corresponding interrupt source is masked. #0 1 The corresponding interrupt source is not masked. #1 EBERR EBERR interrupt mask 22 1 read-write GRA GRA interrupt mask 28 1 read-write 0 The corresponding interrupt source is masked. #0 1 The corresponding interrupt source is not masked. #1 LC LC interrupt mask 21 1 read-write MII MII interrupt mask 23 1 read-write PLR PLR interrupt mask 18 1 read-write RL RL interrupt mask 20 1 read-write RXB RXB interrupt mask 24 1 read-write RXF RXF interrupt mask 25 1 read-write TS_AVAIL TS_AVAIL interrupt mask 16 1 read-write TS_TIMER TS_TIMER interrupt mask 15 1 read-write TXB TXB interrupt mask 26 1 read-write 0 The corresponding interrupt source is masked. #0 1 The corresponding interrupt source is not masked. #1 TXF TXF interrupt mask 27 1 read-write 0 The corresponding interrupt source is masked. #0 1 The corresponding interrupt source is not masked. #1 UN UN interrupt mask 19 1 read-write WAKEUP WAKEUP interrupt mask 17 1 read-write EIR Interrupt Event Register 0x4 32 read-write n 0x0 0x0 BABR Babbling Receive Error 30 1 read-write BABT Babbling Transmit Error 29 1 read-write EBERR Ethernet Bus Error 22 1 read-write GRA Graceful Stop Complete 28 1 read-write LC Late Collision 21 1 read-write MII MII Interrupt. 23 1 read-write PLR Payload receive error 18 1 read-write RL Collision Retry Limit. 20 1 read-write RXB Receive Buffer Interrupt. 24 1 read-write RXF Receive Frame Interrupt 25 1 read-write TS_AVAIL Transmit timestamp available 16 1 read-write TS_TIMER Timestamp timer 15 1 read-write TXB Transmit Buffer Interrupt 26 1 read-write TXF Transmit Frame Interrupt 27 1 read-write UN Transmit FIFO underrun 19 1 read-write WAKEUP Node wake-up request indication 17 1 read-write FTRL Frame Truncation Length 0x1B0 32 read-write n 0x0 0x0 TRUNC_FL Frame truncation length 0 14 read-write GALR Descriptor Group Lower Address Register 0x124 32 read-write n 0x0 0x0 GADDR2 no description available 0 32 read-write GAUR Descriptor Group Upper Address Register 0x120 32 read-write n 0x0 0x0 GADDR1 no description available 0 32 read-write IALR Descriptor Individual Lower Address Register 0x11C 32 read-write n 0x0 0x0 IADDR2 no description available 0 32 read-write IAUR Descriptor Individual Upper Address Register 0x118 32 read-write n 0x0 0x0 IADDR1 no description available 0 32 read-write IEEE_R_ALIGN Frames Received with Alignment Error (IEEE_R_ALIGN) 0x2D4 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_R_CRC Frames Received with CRC Error (IEEE_R_CRC) 0x2D0 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_R_DROP Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments. 0x2C8 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_R_FDXFC Flow Control Pause frames received (IEEE_R_FDXFC) 0x2DC 32 read-write n 0x0 0x0 COUNT Pause frame count 0 16 read-only IEEE_R_FRAME_OK Frames Received OK (IEEE_R_FRAME_OK) 0x2CC 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_R_MACERR Receive Fifo Overflow count (IEEE_R_MACERR) 0x2D8 32 read-write n 0x0 0x0 COUNT Count 0 16 read-only IEEE_R_OCTETS_OK Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields). 0x2E0 32 read-only n 0x0 0x0 COUNT Octet count 0 32 read-only IEEE_T_1COL Frames Transmitted with Single Collision (IEEE_T_1COL) 0x250 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_CSERR Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR) 0x268 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_DEF Frames Transmitted after Deferral Delay (IEEE_T_DEF) 0x258 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_DROP Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable. 0x248 32 read-write n 0x0 0x0 IEEE_T_EXCOL Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL) 0x260 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_FDXFC Flow Control Pause frames transmitted (IEEE_T_FDXFC) 0x270 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_FRAME_OK Frames Transmitted OK (IEEE_T_FRAME_OK) 0x24C 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_LCOL Frames Transmitted with Late Collision (IEEE_T_LCOL) 0x25C 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_MACERR Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR) 0x264 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_MCOL Frames Transmitted with Multiple Collisions (IEEE_T_MCOL) 0x254 32 read-write n 0x0 0x0 COUNT Frame count 0 16 read-only IEEE_T_OCTETS_OK Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields). 0x274 32 read-only n 0x0 0x0 COUNT Octet count 0 32 read-only IEEE_T_SQE Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available. 0x26C 32 read-write n 0x0 0x0 MIBC MIB Control Register 0x64 32 read-write n 0x0 0x0 MIB_CLEAR MIB clear 29 1 read-write MIB_DIS Disable MIB logic 31 1 read-write MIB_IDLE MIB idle 30 1 read-only MMFR MII Management Frame Register 0x40 32 read-write n 0x0 0x0 DATA Management frame data 0 16 read-write OP Operation code 28 2 read-write 00 Write frame operation, but not MII compliant. #00 01 Write frame operation for a valid MII management frame. #01 10 Read frame operation for a valid MII management frame. #10 11 Read frame operation, but not MII compliant. #11 PA PHY address 23 5 read-write RA Register address 18 5 read-write ST Start of frame delimiter 30 2 read-write TA Turn around 16 2 read-write MRBR Maximum Receive Buffer Size Register 0x188 32 read-write n 0x0 0x0 R_BUF_SIZE no description available 4 10 read-write MSCR MII Speed Control Register 0x44 32 read-write n 0x0 0x0 DIS_PRE Disable preamble 7 1 read-write 0 Preamble enabled. #0 1 Preamble (32 ones) is not prepended to the MII management frame. #1 HOLDTIME Holdtime on MDIO output 8 3 read-write 000 1 internal module clock cycle #000 001 2 internal module clock cycles #001 010 3 internal module clock cycles #010 111 8 internal module clock cycles #111 MII_SPEED MII speed 1 6 read-write OPD Opcode/Pause Duration Register 0xEC 32 read-write n 0x0 0x0 OPCODE Opcode field in PAUSE frames 16 16 read-only PAUSE_DUR Pause duration 0 16 read-write PALR Physical Address Lower Register 0xE4 32 read-write n 0x0 0x0 PADDR1 Pause address 0 32 read-write PAUR Physical Address Upper Register 0xE8 32 read-write n 0x0 0x0 PADDR2 no description available 16 16 read-write TYPE Type field in PAUSE frames. 0 16 read-only RACC Receive Accelerator Function Configuration 0x1C4 32 read-write n 0x0 0x0 IPDIS Enable discard of frames with wrong IPv4 header checksum. 1 1 read-write 0 Frames with wrong IPv4 header checksum are not discarded. #0 1 If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). #1 LINEDIS Enable discard of frames with MAC layer errors 6 1 read-write 0 Frames with errors are not discarded. #0 1 Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. #1 PADREM Enable padding removal for short IP frames. 0 1 read-write 0 Padding not removed. #0 1 Any bytes following the IP payload section of the frame are removed from the frame. #1 PRODIS Enable discard of frames with wrong protocol checksum 2 1 read-write 0 Frames with wrong checksum are not discarded. #0 1 If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). #1 SHIFT16 RX FIFO shift-16 7 1 read-write 0 Disabled. #0 1 Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. #1 RAEM Receive FIFO Almost Empty Threshold 0x198 32 read-write n 0x0 0x0 RX_ALMOST_EMPTY Value of the receive FIFO almost empty threshold 0 8 read-write RAFL Receive FIFO Almost Full Threshold 0x19C 32 read-write n 0x0 0x0 RX_ALMOST_FULL Value of the receive FIFO almost full threshold 0 8 read-write RCR Receive Control Register 0x84 32 read-write n 0x0 0x0 BC_REJ Broadcast frame reject 4 1 read-write CFEN MAC control frame enable 15 1 read-write 0 MAC control frames with any opcode other than 0x0001 are accepted and forwarded to the client interface. #0 1 MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. #1 CRCFWD Terminate/forward received CRC 14 1 read-write 0 The CRC field of received frames is transmitted to the user application. #0 1 The CRC field is stripped from the frame. #1 DRT Disable receive on transmit 1 1 read-write 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). #0 1 Disable reception of frames while transmitting (normally used for half duplex mode). #1 FCE Flow control enable 5 1 read-write GRS Graceful receive stopped 31 1 read-only LOOP Internal loopback 0 1 read-write 0 Loopback disabled. #0 1 Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. . #1 MAX_FL Maximum frame length 16 14 read-write MII_MODE Media independent interface mode 2 1 read-write 1 MII or RMII mode, as indicated by the RMII_MODE bit #1 NLC Payload length check disable 30 1 read-write 0 The payload length check is disabled #0 1 The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] bit. #1 PADEN Enable frame padding remove on receive 12 1 read-write 0 No padding is removed on receive by the MAC. #0 1 Padding is removed from received frames. #1 PAUFWD Terminate/forward pause frames. 13 1 read-write 0 Pause frames are terminated and discarded in the MAC. #0 1 Pause frames are forwarded to the user application. #1 PROM Promiscuous mode. All frames are accepted regardless of address matching. 3 1 read-write 0 Disabled #0 1 Enabled #1 RMII_10T no description available 9 1 read-write 0 100 Mbps operation #0 1 10 Mbps operation #1 RMII_MODE RMII mode enable 8 1 read-write 0 MAC configured for MII mode. #0 1 MAC configured for RMII operation. #1 RDAR Receive Descriptor Active Register 0x10 32 read-write n 0x0 0x0 RDAR Receive descriptor active 24 1 read-write RDSR Receive Descriptor Ring Start Register 0x180 32 read-write n 0x0 0x0 R_DES_START no description available 3 29 read-write RMON_R_BC_PKT RMON Rx Broadcast Packets (RMON_R_BC_PKT) 0x288 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_CRC_ALIGN RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN) 0x290 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_FRAG RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG) 0x29C 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_JAB RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB) 0x2A0 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_MC_PKT RMON Rx Multicast Packets (RMON_R_MC_PKT) 0x28C 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_OCTETS RMON Rx Octets (RMON_R_OCTETS) 0x2C4 32 read-only n 0x0 0x0 COUNT Octet count 0 32 read-only RMON_R_OVERSIZE RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE) 0x298 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P1024TO2047 RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047) 0x2BC 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P128TO255 RMON Rx 128 to 255 byte packets (RMON_R_P128TO255) 0x2B0 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P256TO511 RMON Rx 256 to 511 byte packets (RMON_R_P256TO511) 0x2B4 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P512TO1023 RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023) 0x2B8 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P64 RMON Rx 64 byte packets (RMON_R_P64) 0x2A8 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P65TO127 RMON Rx 65 to 127 byte packets (RMON_R_P65TO127) 0x2AC 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_PACKETS RMON Rx packet count (RMON_R_PACKETS) 0x284 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_P_GTE2048 RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048) 0x2C0 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_R_RESVD_0 Reserved (RMON_R_RESVD_0) 0x2A4 32 read-write n 0x0 0x0 RMON_R_UNDERSIZE RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE) 0x294 32 read-write n 0x0 0x0 COUNT Packet count 0 16 read-only RMON_T_BC_PKT RMON Tx Broadcast Packets (RMON_T_BC_PKT) 0x208 32 read-write n 0x0 0x0 TXPKTS Broadcast packets 0 16 read-only RMON_T_COL RMON Tx collision count (RMON_T_COL) 0x224 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_CRC_ALIGN RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN) 0x210 32 read-write n 0x0 0x0 TXPKTS Packets with CRC/align error 0 16 read-only RMON_T_DROP Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable. 0x200 32 read-write n 0x0 0x0 RMON_T_FRAG RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG) 0x21C 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_JAB RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB) 0x220 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_MC_PKT RMON Tx Multicast Packets (RMON_T_MC_PKT) 0x20C 32 read-write n 0x0 0x0 TXPKTS Multicast packets 0 16 read-only RMON_T_OCTETS RMON Tx Octets (RMON_T_OCTETS) 0x244 32 read-only n 0x0 0x0 TXOCTS Octet count 0 32 read-only RMON_T_OVERSIZE RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE) 0x218 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P1024TO2047 RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047) 0x23C 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P128TO255 RMON Tx 128 to 255 byte packets (RMON_T_P128TO255) 0x230 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P256TO511 RMON Tx 256 to 511 byte packets (RMON_T_P256TO511) 0x234 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P512TO1023 RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023) 0x238 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P64 RMON Tx 64 byte packets (RMON_T_P64) 0x228 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P65TO127 RMON Tx 65 to 127 byte packets (RMON_T_P65TO127) 0x22C 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_PACKETS RMON Tx packet count (RMON_T_PACKETS) 0x204 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_P_GTE2048 RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048) 0x240 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RMON_T_UNDERSIZE RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE) 0x214 32 read-write n 0x0 0x0 TXPKTS Packet count 0 16 read-only RSEM Receive FIFO Section Empty Threshold 0x194 32 read-write n 0x0 0x0 RX_SECTION_EMPTY Value of the receive FIFO section empty threshold 0 8 read-write RSFL Receive FIFO Section Full Threshold 0x190 32 read-write n 0x0 0x0 RX_SECTION_FULL Value of receive FIFO section full threshold 0 8 read-write TACC Transmit Accelerator Function Configuration 0x1C0 32 read-write n 0x0 0x0 IPCHK no description available 3 1 read-write 0 Checksum is not inserted. #0 1 If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. #1 PROCHK no description available 4 1 read-write 0 Checksum not inserted. #0 1 If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. #1 SHIFT16 TX FIFO shift-16 0 1 read-write 0 Disabled. #0 1 Indicates to the transmit data FIFO, that the written frames contain two additional octets before the frame data. This means the actual frame starts at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. #1 TAEM Transmit FIFO Almost Empty Threshold 0x1A4 32 read-write n 0x0 0x0 TX_ALMOST_EMPTY Value of transmit FIFO almost empty threshold 0 8 read-write TAFL Transmit FIFO Almost Full Threshold 0x1A8 32 read-write n 0x0 0x0 TX_ALMOST_FULL Value of the transmit FIFO almost full threshold 0 8 read-write TCCR0 Timer Compare Capture Register 0xC18 32 read-write n 0x0 0x0 TCC Timer Capture Compare 0 32 read-write TCCR1 Timer Compare Capture Register 0x122C 32 read-write n 0x0 0x0 TCC Timer Capture Compare 0 32 read-write TCCR2 Timer Compare Capture Register 0x1848 32 read-write n 0x0 0x0 TCC Timer Capture Compare 0 32 read-write TCCR3 Timer Compare Capture Register 0x1E6C 32 read-write n 0x0 0x0 TCC Timer Capture Compare 0 32 read-write TCR Transmit Control Register 0xC4 32 read-write n 0x0 0x0 ADDINS Set MAC address on transmit 8 1 read-write 0 The source MAC address is not modified by the MAC. #0 1 The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. #1 ADDSEL Source MAC address select on transmit 5 3 read-write 000 Node MAC address programmed on PADDR1/2 registers. #000 CRCFWD Forward frame from application with CRC 9 1 read-write 0 TxBD[TC] controls whether the frame has a CRC from the application #0 1 The transmitter does not append any CRC to transmitted frames as it is expecting a frame with CRC from the application. #1 FDEN Full duplex enable 2 1 read-write GTS Graceful transmit stop 0 1 read-write RFC_PAUSE Receive frame control pause 4 1 read-only TFC_PAUSE Transmit frame control pause 3 1 read-write 0 No PAUSE frame transmitted. #0 1 The MAC stops transmission of data frames after the current transmission is complete. #1 TCSR0 Timer Control Status Register 0xC10 32 read-write n 0x0 0x0 TDRE Timer DMA Request Enable 0 1 read-write 0 DMA request is disabled #0 1 DMA request is enabled #1 TF Timer Flag 7 1 read-write 0 Input Capture or Output Compare has not occurred #0 1 Input Capture or Output Compare has occurred #1 TIE Timer interrupt enable 6 1 read-write 0 Interrupt is disabled #0 1 Interrupt is enabled #1 TMODE Timer Mode 2 4 read-write 0000 Timer Channel is disabled. #0000 0001 Timer Channel is configured for Input Capture on rising edge #0001 0010 Timer Channel is configured for Input Capture on falling edge #0010 0011 Timer Channel is configured for Input Capture on both edges #0011 0100 Timer Channel is configured for Output Compare - software only #0100 0101 Timer Channel is configured for Output Compare - toggle output on compare #0101 0110 Timer Channel is configured for Output Compare - clear output on compare #0110 0111 Timer Channel is configured for Output Compare - set output on compare #0111 1010 Timer Channel is configured for Output Compare - clear output on compare, set output on overflow #1010 10x1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow #10x1 1110 Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle #1110 1111 Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle #1111 TCSR1 Timer Control Status Register 0x1220 32 read-write n 0x0 0x0 TDRE Timer DMA Request Enable 0 1 read-write 0 DMA request is disabled #0 1 DMA request is enabled #1 TF Timer Flag 7 1 read-write 0 Input Capture or Output Compare has not occurred #0 1 Input Capture or Output Compare has occurred #1 TIE Timer interrupt enable 6 1 read-write 0 Interrupt is disabled #0 1 Interrupt is enabled #1 TMODE Timer Mode 2 4 read-write 0000 Timer Channel is disabled. #0000 0001 Timer Channel is configured for Input Capture on rising edge #0001 0010 Timer Channel is configured for Input Capture on falling edge #0010 0011 Timer Channel is configured for Input Capture on both edges #0011 0100 Timer Channel is configured for Output Compare - software only #0100 0101 Timer Channel is configured for Output Compare - toggle output on compare #0101 0110 Timer Channel is configured for Output Compare - clear output on compare #0110 0111 Timer Channel is configured for Output Compare - set output on compare #0111 1010 Timer Channel is configured for Output Compare - clear output on compare, set output on overflow #1010 10x1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow #10x1 1110 Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle #1110 1111 Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle #1111 TCSR2 Timer Control Status Register 0x1838 32 read-write n 0x0 0x0 TDRE Timer DMA Request Enable 0 1 read-write 0 DMA request is disabled #0 1 DMA request is enabled #1 TF Timer Flag 7 1 read-write 0 Input Capture or Output Compare has not occurred #0 1 Input Capture or Output Compare has occurred #1 TIE Timer interrupt enable 6 1 read-write 0 Interrupt is disabled #0 1 Interrupt is enabled #1 TMODE Timer Mode 2 4 read-write 0000 Timer Channel is disabled. #0000 0001 Timer Channel is configured for Input Capture on rising edge #0001 0010 Timer Channel is configured for Input Capture on falling edge #0010 0011 Timer Channel is configured for Input Capture on both edges #0011 0100 Timer Channel is configured for Output Compare - software only #0100 0101 Timer Channel is configured for Output Compare - toggle output on compare #0101 0110 Timer Channel is configured for Output Compare - clear output on compare #0110 0111 Timer Channel is configured for Output Compare - set output on compare #0111 1010 Timer Channel is configured for Output Compare - clear output on compare, set output on overflow #1010 10x1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow #10x1 1110 Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle #1110 1111 Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle #1111 TCSR3 Timer Control Status Register 0x1E58 32 read-write n 0x0 0x0 TDRE Timer DMA Request Enable 0 1 read-write 0 DMA request is disabled #0 1 DMA request is enabled #1 TF Timer Flag 7 1 read-write 0 Input Capture or Output Compare has not occurred #0 1 Input Capture or Output Compare has occurred #1 TIE Timer interrupt enable 6 1 read-write 0 Interrupt is disabled #0 1 Interrupt is enabled #1 TMODE Timer Mode 2 4 read-write 0000 Timer Channel is disabled. #0000 0001 Timer Channel is configured for Input Capture on rising edge #0001 0010 Timer Channel is configured for Input Capture on falling edge #0010 0011 Timer Channel is configured for Input Capture on both edges #0011 0100 Timer Channel is configured for Output Compare - software only #0100 0101 Timer Channel is configured for Output Compare - toggle output on compare #0101 0110 Timer Channel is configured for Output Compare - clear output on compare #0110 0111 Timer Channel is configured for Output Compare - set output on compare #0111 1010 Timer Channel is configured for Output Compare - clear output on compare, set output on overflow #1010 10x1 Timer Channel is configured for Output Compare - set output on compare, clear output on overflow #10x1 1110 Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle #1110 1111 Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle #1111 TDAR Transmit Descriptor Active Register 0x14 32 read-write n 0x0 0x0 TDAR Transmit descriptor active 24 1 read-write TDSR Transmit Buffer Descriptor Ring Start Register 0x184 32 read-write n 0x0 0x0 X_DES_START no description available 3 29 read-write TFWR Transmit FIFO Watermark Register 0x144 32 read-write n 0x0 0x0 STRFWD Store and forward enable 8 1 read-write 0 Disabled, the transmission start threshold is programmed in TFWR. #0 1 Enabled. #1 TFWR Transmit FIFO write 0 6 read-write 000000 64 bytes written #000000 000001 64 bytes written #000001 000010 128 bytes written #000010 000011 192 bytes written #000011 111111 4032 bytes written #111111 TGSR Timer Global Status Register 0x604 32 read-write n 0x0 0x0 TF0 Copy of Timer Flag for channel 0 0 1 read-write 0 Timer Flag for Channel 0 is clear #0 1 Timer Flag for Channel 0 is set #1 TF1 Copy of Timer Flag for channel 1 1 1 read-write 0 Timer Flag for Channel 1 is clear #0 1 Timer Flag for Channel 1 is set #1 TF2 Copy of Timer Flag for channel 2 2 1 read-write 0 Timer Flag for Channel 2 is clear #0 1 Timer Flag for Channel 2 is set #1 TF3 Copy of Timer Flag for channel 3 3 1 read-write 0 Timer Flag for Channel 3 is clear #0 1 Timer Flag for Channel 3 is set #1 TIPG Transmit Inter-Packet Gap 0x1AC 32 read-write n 0x0 0x0 IPG Transmit inter-packet gap 0 5 read-write TSEM Transmit FIFO Section Empty Threshold 0x1A0 32 read-write n 0x0 0x0 TX_SECTION_EMPTY Value of the transmit FIFO section empty threshold 0 8 read-write EWM External Watchdog Monitor EWM 0x0 0x0 0x4 registers n CMPH Compare High Register 0x3 8 read-write n 0x0 0x0 COMPAREH no description available 0 8 read-write CMPL Compare Low Register 0x2 8 read-write n 0x0 0x0 COMPAREL no description available 0 8 read-write CTRL Control Register 0x0 8 read-write n 0x0 0x0 ASSIN EWM_in's Assertion State Select. 1 1 read-write EWMEN EWM enable. 0 1 read-write INEN Input Enable. 2 1 read-write SERV Service Register 0x1 8 write-only n 0x0 0x0 SERVICE no description available 0 8 write-only FB FlexBus external bus interface FB 0x0 0x0 0x64 registers n CSAR0 Chip select address register 0x0 32 read-write n 0x0 0x0 BA Base address 16 16 read-write CSAR1 Chip select address register 0xC 32 read-write n 0x0 0x0 BA Base address 16 16 read-write CSAR2 Chip select address register 0x24 32 read-write n 0x0 0x0 BA Base address 16 16 read-write CSAR3 Chip select address register 0x48 32 read-write n 0x0 0x0 BA Base address 16 16 read-write CSAR4 Chip select address register 0x78 32 read-write n 0x0 0x0 BA Base address 16 16 read-write CSAR5 Chip select address register 0xB4 32 read-write n 0x0 0x0 BA Base address 16 16 read-write CSCR0 Chip select control register 0x10 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR1 Chip select control register 0x24 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR2 Chip select control register 0x44 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR3 Chip select control register 0x70 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR4 Chip select control register 0xA8 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR5 Chip select control register 0xEC 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSMR0 Chip select mask register 0x8 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR1 Chip select mask register 0x18 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR2 Chip select mask register 0x34 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR3 Chip select mask register 0x5C 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR4 Chip select mask register 0x90 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR5 Chip select mask register 0xD0 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSPMCR Chip select port multiplexing control register 0x60 32 read-write n 0x0 0x0 GROUP1 FlexBus signal group 1 multiplex control 28 4 read-write 0000 FB_ALE #0000 0001 FB_CS1 #0001 0010 FB_TS #0010 GROUP2 FlexBus signal group 2 multiplex control 24 4 read-write 0000 FB_CS4 #0000 0001 FB_TSIZ0 #0001 0010 FB_BE_31_24 #0010 GROUP3 FlexBus signal group 3 multiplex control 20 4 read-write 0000 FB_CS5 #0000 0001 FB_TSIZ1 #0001 0010 FB_BE_23_16 #0010 GROUP4 FlexBus signal group 4 multiplex control 16 4 read-write 0000 FB_TBST #0000 0001 FB_CS2 #0001 0010 FB_BE_15_8 #0010 GROUP5 FlexBus signal group 5 multiplex control 12 4 read-write 0000 FB_TA #0000 0001 FB_CS3. You must also set CSCRn[AA]. #0001 0010 FB_BE_7_0. You must also set CSCRn[AA]. #0010 FMC Flash Memory Controller FMC 0x0 0x0 0x300 registers n DATAW0S0L Cache Data Storage (lower word) 0x408 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S0U Cache Data Storage (upper word) 0x400 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S1L Cache Data Storage (lower word) 0x614 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S1U Cache Data Storage (upper word) 0x608 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S2L Cache Data Storage (lower word) 0x828 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S2U Cache Data Storage (upper word) 0x818 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S3L Cache Data Storage (lower word) 0xA44 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S3U Cache Data Storage (upper word) 0xA30 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S4L Cache Data Storage (lower word) 0xC68 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S4U Cache Data Storage (upper word) 0xC50 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S5L Cache Data Storage (lower word) 0xE94 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S5U Cache Data Storage (upper word) 0xE78 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S6L Cache Data Storage (lower word) 0x10C8 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S6U Cache Data Storage (upper word) 0x10A8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S7L Cache Data Storage (lower word) 0x1304 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S7U Cache Data Storage (upper word) 0x12E0 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S0L Cache Data Storage (lower word) 0x488 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S0U Cache Data Storage (upper word) 0x480 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S1L Cache Data Storage (lower word) 0x6D4 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S1U Cache Data Storage (upper word) 0x6C8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S2L Cache Data Storage (lower word) 0x928 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S2U Cache Data Storage (upper word) 0x918 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S3L Cache Data Storage (lower word) 0xB84 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S3U Cache Data Storage (upper word) 0xB70 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S4L Cache Data Storage (lower word) 0xDE8 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S4U Cache Data Storage (upper word) 0xDD0 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S5L Cache Data Storage (lower word) 0x1054 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S5U Cache Data Storage (upper word) 0x1038 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S6L Cache Data Storage (lower word) 0x12C8 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S6U Cache Data Storage (upper word) 0x12A8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S7L Cache Data Storage (lower word) 0x1544 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S7U Cache Data Storage (upper word) 0x1520 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S0L Cache Data Storage (lower word) 0x508 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S0U Cache Data Storage (upper word) 0x500 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S1L Cache Data Storage (lower word) 0x794 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S1U Cache Data Storage (upper word) 0x788 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S2L Cache Data Storage (lower word) 0xA28 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S2U Cache Data Storage (upper word) 0xA18 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S3L Cache Data Storage (lower word) 0xCC4 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S3U Cache Data Storage (upper word) 0xCB0 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S4L Cache Data Storage (lower word) 0xF68 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S4U Cache Data Storage (upper word) 0xF50 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S5L Cache Data Storage (lower word) 0x1214 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S5U Cache Data Storage (upper word) 0x11F8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S6L Cache Data Storage (lower word) 0x14C8 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S6U Cache Data Storage (upper word) 0x14A8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S7L Cache Data Storage (lower word) 0x1784 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S7U Cache Data Storage (upper word) 0x1760 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S0L Cache Data Storage (lower word) 0x588 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S0U Cache Data Storage (upper word) 0x580 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S1L Cache Data Storage (lower word) 0x854 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S1U Cache Data Storage (upper word) 0x848 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S2L Cache Data Storage (lower word) 0xB28 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S2U Cache Data Storage (upper word) 0xB18 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S3L Cache Data Storage (lower word) 0xE04 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S3U Cache Data Storage (upper word) 0xDF0 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S4L Cache Data Storage (lower word) 0x10E8 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S4U Cache Data Storage (upper word) 0x10D0 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S5L Cache Data Storage (lower word) 0x13D4 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S5U Cache Data Storage (upper word) 0x13B8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S6L Cache Data Storage (lower word) 0x16C8 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S6U Cache Data Storage (upper word) 0x16A8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S7L Cache Data Storage (lower word) 0x19C4 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S7U Cache Data Storage (upper word) 0x19A0 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write PFAPR Flash Access Protection Register 0x0 32 read-write n 0x0 0x0 M0AP Master 0 Access Protection 0 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M0PFD Master 0 Prefetch Disable 16 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M1AP Master 1 Access Protection 2 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M1PFD Master 1 Prefetch Disable 17 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M2AP Master 2 Access Protection 4 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M2PFD Master 2 Prefetch Disable 18 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M3AP Master 3 Access Protection 6 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M3PFD Master 3 Prefetch Disable 19 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M4AP Master 4 Access Protection 8 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M4PFD Master 4 Prefetch Disable 20 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M5AP Master 5 Access Protection 10 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M5PFD Master 5 Prefetch Disable 21 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M6AP Master 6 Access Protection 12 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M6PFD Master 6 Prefetch Disable 22 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M7AP Master 7 Access Protection 14 2 read-write 00 No access may be performed by this master. #00 01 Only read accesses may be performed by this master. #01 10 Only write accesses may be performed by this master. #10 11 Both read and write accesses may be performed by this master. #11 M7PFD Master 7 Prefetch Disable 23 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 PFB0CR Flash Bank 0 Control Register 0x4 32 read-write n 0x0 0x0 B0DCE Bank 0 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 B0DPE Bank 0 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B0ICE Bank 0 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B0IPE Bank 0 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B0MW Bank 0 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 B0RWSC Bank 0 Read Wait State Control 28 4 read-only B0SEBE Bank 0 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 CINV_WAY Cache Invalidate Way x 20 4 write-only 0 No cache way invalidation for the corresponding cache #0 1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected #1 CLCK_WAY Cache Lock Way x 24 4 read-write 0 Cache way is unlocked and may be displaced #0 1 Cache way is locked and its contents are not displaced #1 CRC Cache Replacement Control 5 3 read-write 000 LRU replacement algorithm per set across all four ways #000 010 Independent LRU with ways [0-1] for ifetches, [2-3] for data #010 011 Independent LRU with ways [0-2] for ifetches, [3] for data #011 S_B_INV Invalidate Prefetch Speculation Buffer 19 1 write-only 0 Speculation buffer and single entry buffer are not affected. #0 1 Invalidate (clear) speculation buffer and single entry buffer. #1 PFB1CR Flash Bank 1 Control Register 0x8 32 read-write n 0x0 0x0 B1DCE Bank 1 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 B1DPE Bank 1 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B1ICE Bank 1 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B1IPE Bank 1 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B1MW Bank 1 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 B1RWSC Bank 1 Read Wait State Control 28 4 read-only B1SEBE Bank 1 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 TAGVDW0S0 Cache Tag Storage 0x200 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S1 Cache Tag Storage 0x304 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S2 Cache Tag Storage 0x40C 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S3 Cache Tag Storage 0x518 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S4 Cache Tag Storage 0x628 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S5 Cache Tag Storage 0x73C 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S6 Cache Tag Storage 0x854 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S7 Cache Tag Storage 0x970 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S0 Cache Tag Storage 0x240 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S1 Cache Tag Storage 0x364 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S2 Cache Tag Storage 0x48C 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S3 Cache Tag Storage 0x5B8 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S4 Cache Tag Storage 0x6E8 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S5 Cache Tag Storage 0x81C 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S6 Cache Tag Storage 0x954 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S7 Cache Tag Storage 0xA90 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S0 Cache Tag Storage 0x280 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S1 Cache Tag Storage 0x3C4 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S2 Cache Tag Storage 0x50C 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S3 Cache Tag Storage 0x658 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S4 Cache Tag Storage 0x7A8 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S5 Cache Tag Storage 0x8FC 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S6 Cache Tag Storage 0xA54 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S7 Cache Tag Storage 0xBB0 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S0 Cache Tag Storage 0x2C0 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S1 Cache Tag Storage 0x424 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S2 Cache Tag Storage 0x58C 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S3 Cache Tag Storage 0x6F8 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S4 Cache Tag Storage 0x868 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S5 Cache Tag Storage 0x9DC 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S6 Cache Tag Storage 0xB54 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S7 Cache Tag Storage 0xCD0 32 read-write n 0x0 0x0 tag 13-bit tag for cache entry 6 13 read-write valid 1-bit valid for cache entry 0 1 read-write FTFL Flash Memory Interface FTFL 0x0 0x0 0x18 registers n FTFL 18 Read_Collision 19 FCCOB0 Flash Common Command Object Registers 0x1A 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x13 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB2 Flash Common Command Object Registers 0xD 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB3 Flash Common Command Object Registers 0x8 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB4 Flash Common Command Object Registers 0x40 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB5 Flash Common Command Object Registers 0x35 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x2B 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x22 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB8 Flash Common Command Object Registers 0x76 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB9 Flash Common Command Object Registers 0x67 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOBA Flash Common Command Object Registers 0x59 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOBB Flash Common Command Object Registers 0x4C 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCNFG Flash Configuration Register 0x1 8 read-write n 0x0 0x0 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 EEERDY no description available 0 1 read-only 0 For devices with FlexNVM: FlexRAM is not available for EEPROM operation. #0 1 For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes to the FlexRAM clear EEERDY and launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 PFLSH FTFL configuration 2 1 read-only 0 For devices with FlexNVM: FTFL configured for FlexMemory that supports data flash and/or EEPROM For devices with program flash only: Reserved #0 1 For devices with FlexNVM: Reserved For devices with program flash only: FTFL configured for program flash only, without support for data flash and/or EEPROM #1 RAMRDY RAM Ready 1 1 read-only 0 For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available. #0 1 For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFL read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 SWAP Swap 3 1 read-only 0 Physical program flash 0 is located at relative address 0x0000 #0 1 If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH flag is not set, physical program flash 0 is located at relative address 0x0000 #1 FDPROT Data Flash Protection Register 0x17 8 read-write n 0x0 0x0 DPROT Data Flash Region Protect 0 8 read-write 0 Data Flash region is protected #0 1 Data Flash region is not protected #1 FEPROT EEPROM Protection Register 0x16 8 read-write n 0x0 0x0 EPROT EEPROM Region Protect 0 8 read-write 0 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected #0 1 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected #1 FOPT Flash Option Register 0x3 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FPROT0 Program Flash Protection Registers 0x56 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT1 Program Flash Protection Registers 0x43 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT2 Program Flash Protection Registers 0x31 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT3 Program Flash Protection Registers 0x20 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FSEC Flash Security Register 0x2 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN Mass Erase Enable Bits 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 00 MCU security status is secure #00 01 MCU security status is secure #01 10 MCU security status is unsecure (The standard shipping condition of the FTFL is unsecure.) #10 11 MCU security status is secure #11 FSTAT Flash Status Register 0x0 8 read-write n 0x0 0x0 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 FTFL command or EEPROM file system operation in progress #0 1 FTFL command or EEPROM file system operation has completed #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only RDCOLERR FTFL Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 FTFL_FlashConfig Flash configuration field FTFL_FlashConfig 0x0 0x0 0x10 registers n NV_BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_FDPROT Non-volatile D-Flash Protection Register 0xF 8 read-only n 0x0 0x0 DPROT D-Flash Region Protect 0 8 read-only NV_FEPROT Non-volatile EERAM Protection Register 0xE 8 read-only n 0x0 0x0 EPROT no description available 0 8 read-only NV_FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 EZPORT_DIS no description available 1 1 read-only 00 EzPort operation is disabled #00 01 EzPort operation is enabled #01 LPBOOT no description available 0 1 read-only 00 Low-power boot #00 01 Normal boot #01 NV_FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FTM0 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM0 62 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C2SC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C3SC Channel (n) Status and Control 0x6C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C4SC Channel (n) Status and Control 0x98 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C5SC Channel (n) Status and Control 0xCC 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C6SC Channel (n) Status and Control 0x108 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C6V Channel (n) Value 0x128 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C7SC Channel (n) Status and Control 0x14C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C7V Channel (n) Value 0x170 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM1 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM1 63 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM2 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM2 64 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 I2C0 Inter-Integrated Circuit I2C 0x0 0x0 0xC registers n I2C0 24 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 SAD SMBus address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C interrupt enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master mode select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit mode select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit acknowledge enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte. #0 1 No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written. #1 WUEN Wakeup enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave address 0 3 read-write ADEXT Address extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General call address enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High drive select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range address matching enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave baud rate control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR Clock rate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write n 0x0 0x0 FLT I2C programmable filter factor 0 5 read-write 0 No filter/bypass #0 RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range slave address 1 7 read-write S I2C Status Register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed as a slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range address match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave read/write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer complete flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus alert response address enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 SHTF1 SCL high timeout flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL high timeout flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 interrupt enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C address enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL low timeout flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout counter clock select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 I2C1 Inter-Integrated Circuit I2C 0x0 0x0 0xC registers n I2C1 25 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 SAD SMBus address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C interrupt enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master mode select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit mode select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit acknowledge enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte. #0 1 No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written. #1 WUEN Wakeup enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave address 0 3 read-write ADEXT Address extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General call address enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High drive select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range address matching enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave baud rate control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR Clock rate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write n 0x0 0x0 FLT I2C programmable filter factor 0 5 read-write 0 No filter/bypass #0 RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range slave address 1 7 read-write S I2C Status Register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed as a slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range address match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave read/write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer complete flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus alert response address enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 SHTF1 SCL high timeout flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL high timeout flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 interrupt enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C address enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL low timeout flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout counter clock select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 I2S0 Synchronous Serial Interface I2S0 0x0 0x0 0x5C registers n I2S0 79 ACADD I2S AC97 Command Address Register 0x3C 32 read-write n 0x0 0x0 ACADD AC97 Command Address. 0 19 read-write ACCDIS I2S AC97 Channel Disable Register 0x58 32 read-write n 0x0 0x0 ACCDIS AC97 Channel Disable. 0 10 write-only 0 Write has no effect. #0 1 Write disables the corresponding data channel. #1 ACCEN I2S AC97 Channel Enable Register 0x54 32 read-write n 0x0 0x0 ACCEN AC97 Channel Enable. 0 10 write-only 0 Write has no effect. #0 1 Write enables the corresponding data channel. #1 ACCST I2S AC97 Channel Status Register 0x50 32 read-only n 0x0 0x0 ACCST AC97 Channel Status. 0 10 read-only 0 Data channel disabled. #0 1 Data channel enabled. #1 ACDAT I2S AC97 Command Data Register 0x40 32 read-write n 0x0 0x0 ACDAT AC97 Command Data. 0 20 read-write ACNT I2S AC97 Control Register 0x38 32 read-write n 0x0 0x0 AC97EN AC97 Mode Enable. 0 1 read-write 0 AC97 mode disabled. #0 1 I2S in AC97 mode. #1 FRDIV Frame Rate Divider. 5 6 read-write FV Fixed/Variable Operation. 1 1 read-write 0 AC97 Fixed Mode #0 1 AC97 Variable Mode. #1 RD Read Command. 3 1 read-write 0 Next frame will not have a Read Command. #0 1 Next frame will have a Read Command. #1 TIF Tag in FIFO. 2 1 read-write 0 Tag info stored in ATAG register. #0 1 Tag info stored in ATAG register and Rx FIFO 0. #1 WR Write Command. 4 1 read-write 0 Next frame will not have a Write Command. #0 1 Next frame will have a Write Command. #1 ATAG I2S AC97 Tag Register 0x44 32 read-write n 0x0 0x0 ATAG AC97 Tag Value. 0 16 read-write CR I2S Control Register 0x10 32 read-write n 0x0 0x0 CLKIST Clock Idle State. 9 1 read-write 0 Clock idle state is `0'. #0 1 Clock idle state is `1'. #1 I2SEN I2S Enable. 0 1 read-write 0 I2S is disabled. #0 1 I2S is enabled. #1 I2SMODE I2S Mode Select 5 2 read-write 00 Normal mode #00 01 I2S master mode #01 10 I2S slave mode #10 11 Normal mode #11 NET Network Mode. 3 1 read-write 0 Network mode not selected. #0 1 Network mode selected. #1 RE Receive Enable. 2 1 read-write 0 Receive section disabled. #0 1 Receive section enabled. #1 RFRCLKDIS Receive Frame Clock Disable. 11 1 read-write 0 Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may be required when Frame-sync and Clocks are required from I2S, even when no data is to be received. #0 1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where receiver is already disabled in current or previous frames. #1 SYN Synchronous Mode. 4 1 read-write 0 Asynchronous mode selected. #0 1 Synchronous mode selected. #1 SYNCTXFS no description available 12 1 read-write 0 CR[TE] not latched with FS occurrence and used directly for transmitter enable/disable. #0 1 CR[TE] latched with FS occurrence and latched-TE used for transmitter enable/disable. #1 SYSCLKEN System Clock (Oversampling Clock) Enable. 7 1 read-write 0 Network clock not output on SRCK port. #0 1 Network clock output on SRCK port. #1 TCHEN Two-Channel Operation Enable. 8 1 read-write 0 Two-channel mode disabled. #0 1 Two-channel mode enabled. #1 TE Transmit Enable. 1 1 read-write 0 Transmit section disabled. #0 1 Transmit section enabled. #1 TFRCLKDIS Transmit Frame Clock Disable. 10 1 read-write 0 Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may be required when frame-sync and clocks are required from I2S, even when no data is to be received. #0 1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where transmitter is already disabled in current or previous frames. #1 FCSR I2S FIFO Control/Status Register 0x2C 32 read-write n 0x0 0x0 RFCNT0 Receive FIFO Counter 0. 12 4 read-write 0000 0 data word in receive FIFO. #0000 0001 1 data word in receive FIFO. #0001 0010 2 data word in receive FIFO. #0010 0011 3 data word in receive FIFO. #0011 0100 4 data word in receive FIFO. #0100 0101 5 data word in receive FIFO. #0101 0110 6 data word in receive FIFO. #0110 0111 7 data word in receive FIFO. #0111 1000 8 data word in receive FIFO. #1000 1001 9 data word in receive FIFO. #1001 1010 10 data word in receive FIFO. #1010 1011 11 data word in receive FIFO. #1011 1100 12 data word in receive FIFO. #1100 1101 13 data word in receive FIFO. #1101 1110 14 data word in receive FIFO. #1110 1111 15 data word in receive FIFO. #1111 RFCNT1 Receive FIFO Counter1. 28 4 read-write 0000 0 data word in receive FIFO. #0000 0001 1 data word in receive FIFO. #0001 0010 2 data word in receive FIFO. #0010 0011 3 data word in receive FIFO. #0011 0100 4 data word in receive FIFO. #0100 0101 5 data word in receive FIFO. #0101 0110 6 data word in receive FIFO. #0110 0111 7 data word in receive FIFO. #0111 1000 8 data word in receive FIFO. #1000 1001 9 data word in receive FIFO. #1001 1010 10 data word in receive FIFO. #1010 1011 11 data word in receive FIFO. #1011 1100 12 data word in receive FIFO. #1100 1101 13 data word in receive FIFO. #1101 1110 14 data word in receive FIFO. #1110 1111 15 data word in receive FIFO. #1111 RFWM0 Receive FIFO Full WaterMark 0. 4 4 read-write 0001 RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO = 1,2.....15 data words #0001 0010 RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words #0010 0011 RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words #0011 0100 RFF set when more than or equal to 4 data word have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words #0100 0101 RFF set when more than or equal to 5 data word have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words #0101 0110 RFF set when more than or equal to 6 data word have been written to the Receive. Set when RxFIFO = 6,7......15 data words #0110 0111 RFF set when more than or equal to 7 data word have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words #0111 1000 RFF set when more than or equal to 8 data word have been written to the Receive FIFO. Set when RxFIFO = 8,9......15 data words #1000 1001 RFF set when more than or equal to 9 data word have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words #1001 1010 RFF set when more than or equal to 10 data word have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words #1010 1011 RFF set when more than or equal to 11 data word have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words #1011 1100 RFF set when more than or equal to 12 data word have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words #1100 1101 RFF set when more than or equal to 13 data word have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words #1101 1110 RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words #1110 1111 RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words #1111 RFWM1 Receive FIFO Full WaterMark 1. 20 4 read-write 0001 RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO = 1,2.....15 data words #0001 0010 RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words #0010 0011 RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words #0011 0100 RFF set when more than or equal to 4 data word have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words #0100 0101 RFF set when more than or equal to 5 data word have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words #0101 0110 RFF set when more than or equal to 6 data word have been written to the Receive. Set when RxFIFO = 6,7......15 data words #0110 0111 RFF set when more than or equal to 7 data word have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words #0111 1000 RFF set when more than or equal to 8 data word have been written to the Receive FIFO. Set when RxFIFO = 8,9......15 data words #1000 1001 RFF set when more than or equal to 9 data word have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words #1001 1010 RFF set when more than or equal to 10 data word have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words #1010 1011 RFF set when more than or equal to 11 data word have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words #1011 1100 RFF set when more than or equal to 12 data word have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words #1100 1101 RFF set when more than or equal to 13 data word have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words #1101 1110 RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words #1110 1111 RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words #1111 TFCNT0 Transmit FIFO Counter 0. 8 4 read-write 0000 0 data word in transmit FIFO. #0000 0001 1 data word in transmit FIFO. #0001 0010 2 data word in transmit FIFO. #0010 0011 3 data word in transmit FIFO. #0011 0100 4 data word in transmit FIFO. #0100 0101 5 data word in transmit FIFO. #0101 0110 6 data word in transmit FIFO. #0110 0111 7 data word in transmit FIFO. #0111 1000 8 data word in transmit FIFO. #1000 1001 9 data word in transmit FIFO. #1001 1010 10 data word in transmit FIFO. #1010 1011 11 data word in transmit FIFO. #1011 1100 12 data word in transmit FIFO. #1100 1101 13 data word in transmit FIFO. #1101 1110 14 data word in transmit FIFO. #1110 1111 15 data word in transmit FIFO. #1111 TFCNT1 Transmit FIFO Counter1. 24 4 read-write 0000 0 data word in transmit FIFO. #0000 0001 1 data word in transmit FIFO. #0001 0010 2 data word in transmit FIFO. #0010 0011 3 data word in transmit FIFO. #0011 0100 4 data word in transmit FIFO. #0100 0101 5 data word in transmit FIFO. #0101 0110 6 data word in transmit FIFO. #0110 0111 7 data word in transmit FIFO. #0111 1000 8 data word in transmit FIFO. #1000 1001 9 data word in transmit FIFO. #1001 1010 10 data word in transmit FIFO. #1010 1011 11 data word in transmit FIFO. #1011 1100 12 data word in transmit FIFO. #1100 1101 13 data word in transmit FIFO. #1101 1110 14 data word in transmit FIFO. #1110 1111 15 data word in transmit FIFO. #1111 TFWM0 Transmit FIFO Empty WaterMark 0. 0 4 read-write 0001 TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 14 data. #0001 0010 TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 13 data. #0010 0011 TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 12 data. #0011 0100 TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 11 data. #0100 0101 TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 10 data. #0101 0110 TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 9 data. #0110 0111 TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 8 data. #0111 1000 TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 7 data. #1000 1001 TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 6 data. #1001 1010 TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 5 data. #1010 1011 TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 4 data. #1011 1100 TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 3 data. #1100 1101 TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 2 data. #1101 1110 TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 1 data. #1110 1111 TFE set when there are more than or equal to 15 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 0 data. #1111 TFWM1 Transmit FIFO Empty WaterMark 1. 16 4 read-write 0001 TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 14 data. #0001 0010 TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 13 data. #0010 0011 TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 12 data. #0011 0100 TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 11 data. #0100 0101 TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 10 data. #0101 0110 TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 9 data. #0110 0111 TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 8 data. #0111 1000 TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 7 data. #1000 1001 TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 6 data. #1001 1010 TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 5 data. #1010 1011 TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 4 data. #1011 1100 TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 3 data. #1100 1101 TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 2 data. #1101 1110 TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 1 data. #1110 1111 TFE set when there are more than or equal to 15 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 0 data. #1111 IER I2S Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 CMDAUEN Enable Bit. 18 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 CMDDUEN Enable Bit. 17 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RDMAE Receive DMA Enable. 22 1 read-write 0 I2S receiver DMA requests disabled. #0 1 I2S receiver DMA requests enabled. #1 RDR0EN Enable Bit. 14 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RDR1EN Enable Bit. 15 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RFF0EN Enable Bit. 2 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RFF1EN Enable Bit. 3 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RFRC_EN Enable Bit. 24 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RFSEN Enable Bit. 6 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RIE Receive Interrupt Enable. 21 1 read-write 0 I2S receiver interrupt requests disabled. #0 1 I2S receiver interrupt requests enabled. #1 RLSEN Enable Bit. 4 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 ROE0EN Enable Bit. 10 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 ROE1EN Enable Bit. 11 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 RXTEN Enable Bit. 16 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TDE0EN Enable Bit. 12 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TDE1EN Enable Bit. 13 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TDMAE Transmit DMA Enable. 20 1 read-write 0 I2S transmitter DMA requests disabled. #0 1 I2S transmitter DMA requests enabled. #1 TFE0EN Enable Bit. 0 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TFE1EN Enable Bit. 1 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TFRC_EN Enable Bit. 23 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TFSEN Enable Bit. 7 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TIE Transmit Interrupt Enable. 19 1 read-write 0 I2S transmitter interrupt requests disabled. #0 1 I2S transmitter interrupt requests enabled. #1 TLSEN Enable Bit. 5 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TUE0EN Enable Bit. 8 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 TUE1EN Enable Bit. 9 1 read-write 0 Corresponding status bit cannot issue interrupt. #0 1 Corresponding status bit can issue interrupt. #1 ISR I2S Interrupt Status Register 0x14 32 read-write n 0x0 0x0 CMDAU Command Address Register Updated. 18 1 read-only 0 No change in ACADD register. #0 1 ACADD register updated with different value. #1 CMDDU Command Data Register Updated. 17 1 read-only 0 No change in ACDAT register. #0 1 ACDAT register updated with different value. #1 RDR0 Receive Data Ready 0. 14 1 read-only 0 No new data for core to read. #0 1 New data for core to read. #1 RDR1 Receive Data Ready 1. 15 1 read-only 0 No new data for core to read. #0 1 New data for core to read. #1 RFF0 Receive FIFO Full 0. 2 1 read-only 0 Space available in receive FIFO0. #0 1 Receive FIFO0 is full. #1 RFF1 Receive FIFO Full 1. 3 1 read-only 0 Space available in receive FIFO1. #0 1 Receive FIFO1 is full. #1 RFRC Receive Frame Complete. 24 1 read-write 0 End of frame not reached. #0 1 End of frame reached after disabling CR[RE] or disabling CR[RFRCLKDIS], when receiver is already disabled. #1 RFS Receive Frame Sync. 6 1 read-only 0 No occurrence of receive frame sync. #0 1 Receive frame sync occurred during reception of next word in RX registers. #1 RLS Receive Last Time Slot. 4 1 read-only 0 Current time slot is not last time slot of frame. #0 1 Current time slot is the last receive time slot of frame. #1 ROE0 Receiver Overrun Error 0. 10 1 read-write 0 No overrun detected #0 1 Receiver overrun error occurred #1 ROE1 Receiver Overrun Error 1. 11 1 read-write 0 No overrun detected #0 1 Receiver overrun error occurred #1 RXT Receive Tag Updated. 16 1 read-only 0 No change in ATAG register. #0 1 ATAG register updated with different value. #1 TDE0 Transmit Data Register Empty 0. 12 1 read-only 0 Data available for transmission. #0 1 Data needs to be written by the core for transmission. #1 TDE1 Transmit Data Register Empty 1. 13 1 read-only 0 Data available for transmission. #0 1 Data needs to be written by the core for transmission. #1 TFE0 Transmit FIFO Empty 0. 0 1 read-only 0 Transmit FIFO0 has data for transmission. #0 1 Transmit FIFO0 is empty. #1 TFE1 Transmit FIFO Empty 1. 1 1 read-only 0 Transmit FIFO1 has data for transmission. #0 1 Transmit FIFO1 is empty. #1 TFS Transmit Frame Sync. 7 1 read-only 0 No occurrence of transmit frame sync. #0 1 Transmit frame sync occurred during transmission of last word written to TX registers. #1 TLS Transmit Last Time Slot. 5 1 read-only 0 Current time slot is not last time slot of frame. #0 1 Current time slot is the last transmit time slot of frame. #1 TRFC Transmit Frame Complete. 23 1 read-write 0 End of frame not reached. #0 1 End of frame reached after disabling CR[TE] or disabling CR[TFRCLKDIS], when transmitter is already disabled. #1 TUE0 Transmitter Underrun Error 1. 8 1 read-write 0 No underrun detected #0 1 Transmitter underrun error occurred #1 TUE1 Transmitter Underrun Error 1. 9 1 read-write 0 No underrun detected #0 1 Transmitter underrun error occurred #1 RCCR I2S Receive Clock Control Registers 0x28 32 read-write n 0x0 0x0 DC Frame Rate Divider Control. 8 5 read-write DIV2 Divide By 2. 18 1 read-write 0 Divider bypassed. #0 1 Divider used to divide clock by 2. #1 PM Prescaler Modulus Select. 0 8 read-write PSR Prescaler Range. 17 1 read-write 0 Prescaler bypassed. #0 1 Prescaler used to divide clock by 8. #1 WL Word Length Control. 13 4 read-write 0000 Number of Bits/Word: 2; Supported in Implementation: No. #0000 0001 Number of Bits/Word: 4; Supported in Implementation: No. #0001 0010 Number of Bits/Word: 6; Supported in Implementation: No. #0010 0011 Number of Bits/Word: 8; Supported in Implementation: Yes. #0011 0100 Number of Bits/Word: 10; Supported in Implementation: Yes. #0100 0101 Number of Bits/Word: 12; Supported in Implementation: Yes. #0101 0110 Number of Bits/Word: 14; Supported in Implementation: No. #0110 0111 Number of Bits/Word: 16; Supported in Implementation: Yes. #0111 1000 Number of Bits/Word: 18; Supported in Implementation: Yes. #1000 1001 Number of Bits/Word: 20; Supported in Implementation: Yes. #1001 1010 Number of Bits/Word: 22; Supported in Implementation: Yes. #1010 1011 Number of Bits/Word: 24; Supported in Implementation: Yes. #1011 1100 Number of Bits/Word: 26; Supported in Implementation: No. #1100 1101 Number of Bits/Word: 28; Supported in Implementation: No. #1101 1110 Number of Bits/Word: 30; Supported in Implementation: No. #1110 1111 Number of Bits/Word: 32; Supported in Implementation: No. #1111 RCR I2S Receive Configuration Register 0x20 32 read-write n 0x0 0x0 REFS Receive Early Frame Sync. 0 1 read-write 0 Receive frame sync initiated as the first bit of data is received. #0 1 Receive frame sync is initiated one bit before the data is received. #1 RFDIR Receive Frame Direction. 6 1 read-write 0 Frame Sync is external. #0 1 Frame Sync generated internally. #1 RFEN0 Receive FIFO Enable 0. 7 1 read-write 0 Receive FIFO 0 disabled. #0 1 Receive FIFO 0 enabled. #1 RFEN1 Receive FIFO Enable 1. 8 1 read-write 0 Receive FIFO 1 disabled. #0 1 Receive FIFO 1 enabled. #1 RFSI Receive Frame Sync Invert. 2 1 read-write 0 Receive frame sync is active high. #0 1 Receive frame sync is active low. #1 RFSL Receive Frame Sync Length. 1 1 read-write 0 Receive frame sync is one-word long. #0 1 Receive frame sync is one-clock-bit long. #1 RSCKP Receive Clock Polarity. 3 1 read-write 0 Data latched on falling edge of bit clock. #0 1 Data latched on rising edge of bit clock. #1 RSHFD Receive Shift Direction. 4 1 read-write 0 Data received MSB first. #0 1 Data received LSB first. #1 RXBIT0 Receive Bit 0. 9 1 read-write 0 Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (MSB aligned). #0 1 Shifting with respect to bit 0 of receive shift register (LSB aligned). #1 RXDIR Receive Clock Direction. 5 1 read-write 0 Receive Clock is external. #0 1 Receive Clock generated internally. #1 RXEXT Receive Data Extension. 10 1 read-write 0 Sign extension turned off. #0 1 Sign extension turned on. #1 RMSK I2S Receive Time Slot Mask Register 0x4C 32 read-write n 0x0 0x0 RMSK Receive Mask. 0 32 read-write 0 Valid Time Slot. #0 1 Time Slot masked (no data received in this time slot). #1 RX0 I2S Receive Data Registers 0 0x8 32 read-write n 0x0 0x0 RX0 I2S Receive Data 0 32 read-write RX1 I2S Receive Data Registers 1 0xC 32 read-write n 0x0 0x0 RX1 I2S Receive Data 0 32 read-write TCCR I2S Transmit Clock Control Registers 0x24 32 read-write n 0x0 0x0 DC Frame Rate Divider Control. 8 5 read-write DIV2 Divide By 2. 18 1 read-write 0 Divider bypassed. #0 1 Divider used to divide clock by 2. #1 PM Prescaler Modulus Select. 0 8 read-write PSR Prescaler Range. 17 1 read-write 0 Prescaler bypassed. #0 1 Prescaler used to divide clock by 8. #1 WL Word Length Control. 13 4 read-write 0000 Reserved. Do not program this value. #0000 0001 Reserved. Do not program this value. #0001 0010 Reserved. Do not program this value. #0010 0011 8 #0011 0100 10 #0100 0101 12 #0101 0110 Reserved. Do not program this value. #0110 0111 16 #0111 1000 18 #1000 1001 20 #1001 1010 22 #1010 1011 24 #1011 1100 Reserved. Do not program this value. #1100 1101 Reserved. Do not program this value. #1101 1110 Reserved. Do not program this value. #1110 1111 Reserved. Do not program this value. #1111 TCR I2S Transmit Configuration Register 0x1C 32 read-write n 0x0 0x0 TEFS Transmit Early Frame Sync. 0 1 read-write 0 Transmit frame sync initiated as the first bit of data is transmitted. #0 1 Transmit frame sync is initiated one bit before the data is transmitted. #1 TFDIR Transmit Frame Direction. 6 1 read-write 0 Frame sync is external. #0 1 Frame sync generated internally. #1 TFEN0 Transmit FIFO Enable 0. 7 1 read-write 0 Transmit FIFO 0 disabled. #0 1 Transmit FIFO 0 enabled. #1 TFEN1 Transmit FIFO Enable 1. 8 1 read-write 0 Transmit FIFO 1 disabled. #0 1 Transmit FIFO 1 enabled. #1 TFSI Transmit Frame Sync Invert. 2 1 read-write 0 Transmit frame sync is active high. #0 1 Transmit frame sync is active low. #1 TFSL Transmit Frame Sync Length. 1 1 read-write 0 Transmit frame sync is one-word long. #0 1 Transmit frame sync is one-clock-bit long. #1 TSCKP Transmit Clock Polarity. 3 1 read-write 0 Data clocked out on rising edge of bit clock. #0 1 Data clocked out on falling edge of bit clock. #1 TSHFD Transmit Shift Direction. 4 1 read-write 0 Data transmitted MSB first. #0 1 Data transmitted LSB first. #1 TXBIT0 Transmit Bit 0. 9 1 read-write 0 Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (MSB aligned). #0 1 Shifting with respect to bit 0 of transmit shift register (LSB aligned). #1 TXDIR Transmit clock direction 5 1 read-write 0 Transmit clock is external. #0 1 Transmit clock generated internally #1 TMSK I2S Transmit Time Slot Mask Register 0x48 32 read-write n 0x0 0x0 TMSK Transmit Mask. 0 32 read-write 0 Valid Time Slot. #0 1 Time Slot masked (no data transmitted in this time slot). #1 TX0 I2S Transmit Data Registers 0 0x0 32 read-write n 0x0 0x0 TX0 I2S transmit data 0 32 read-write TX1 I2S Transmit Data Registers 1 0x4 32 read-write n 0x0 0x0 TX1 I2S transmit data 0 32 read-write LCD Segment Liquid Crystal Display LCD 0x0 0x0 0x60 registers n LCD 86 AR LCD auxiliary register 0x4 32 read-write n 0x0 0x0 ALT Alternate display mode 6 1 read-write 0 Normal display mode. #0 1 Alternate display mode. #1 BLANK Blank display mode 5 1 read-write 0 Normal or alternate display mode. #0 1 Blank display mode. #1 BLINK Blink command 7 1 read-write 0 Disables blinking. #0 1 Starts blinking at blinking frequency specified by LCD blink rate calculation. #1 BMODE Blink mode 3 1 read-write 0 Display blank during the blink period. #0 1 Display alternate display during blink period (Ignored if duty is 5 or greater). #1 BRATE Blink-rate configuration 0 3 read-write LCDIF LCD frame frequency interrupt flag 15 1 read-write 0 Frame frequency interrupt condition has not occurred. #0 1 The start of LCD controller frame has occurred. #1 BPENH LCD backplane enable register 0x4C 32 read-write n 0x0 0x0 BPEN Backplane enable 0 32 read-write 0 Frontplane operation enabled on LCD_Pn. #0 1 Backplane operation enabled on LCD_Pn. #1 BPENL LCD backplane enable register 0x30 32 read-write n 0x0 0x0 BPEN Backplane enable 0 32 read-write 0 Frontplane operation enabled on LCD_Pn. #0 1 Backplane operation enabled on LCD_Pn. #1 FDCR LCD fault detect control register 0x8 32 read-write n 0x0 0x0 FDBPEN Fault detect backplane enable 6 1 read-write 0 Type of the selected pin under fault detect test is frontplane. #0 1 Type of the selected pin under fault detect test is backplane. #1 FDEN Fault detect enable 7 1 read-write 0 Disable fault detection. #0 1 Enable fault detection. #1 FDPINID Fault detect pin ID 0 6 read-write 0 Fault detection for LCD_P0 pin. #0 1 Fault detection for LCD_P1 pin. #1 FDPRS Fault detect clock prescaler 12 3 read-write 0 1/1 bus clock. #0 1 1/2 bus clock. #1 FDSWW Fault detect sample window width 9 3 read-write 0 Sample window width is 4 sample clock cycles. #0 1 Sample window width is 8 sample clock cycles. #1 FDSR LCD fault detect status register 0xC 32 read-write n 0x0 0x0 FDCF Fault detection complete flag 15 1 read-write 0 Fault detection is not completed. #0 1 Fault detection is completed. #1 FDCNT Fault detect counter 0 8 read-only 0 No "one" samples. #0 1 1 "one" samples. #1 GCR LCD general control register 0x0 32 read-write n 0x0 0x0 ALTDIV LCD alternate clock divider 12 2 read-write 0 Divide factor = 1 (No divide) #0 1 Divide factor = 8 #1 CPSEL Charge pump or resistor bias select 23 1 read-write 0 LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.) #0 1 LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.) #1 DUTY LCD duty select 0 3 read-write 000 Use 1 BP (1/1 duty cycle). #000 001 Use 2 BP (1/2 duty cycle). #001 010 Use 3 BP (1/3 duty cycle). #010 011 Use 4 BP (1/4 duty cycle). (Default) #011 100 Use 5 BP (1/5 duty cycle). #100 101 Use 6 BP (1/6 duty cycle). #101 110 Use 7 BP (1/7 duty cycle). #110 111 Use 8 BP (1/8 duty cycle). #111 FDCIEN LCD fault detection complete interrupt enable 14 1 read-write 0 No interrupt request is generated by this event. #0 1 When a fault is detected and FDCF bit is set, this event causes an interrupt request. #1 HREFSEL High reference select 22 1 read-write 0 Divide input, VIREG = 1.0 V for 3 V glass. #0 1 Do not divide the input, VIREG = 1.67 V for 5 V glass. #1 LADJ Load adjust 20 2 read-write LCDEN LCD driver enable 7 1 read-write 0 All frontplane and backplane pins are disabled. The LCD controller system is also disabled, and all LCD waveform generation clocks are stopped. VLL3 is connected to VDD internally. #0 1 LCD controller driver system is enabled, and frontplane and backplane waveforms are generated. All LCD pins, LCD_Pn, enabled using the LCD pin enable register, output an LCD driver waveform.The backplane pins output an LCD driver backplane waveform based on the settings of DUTY[2:0]. Charge pump or resistor bias is enabled. #1 LCDIEN LCD frame frequency interrupt enable 15 1 read-write 0 No interrupt request is generated by this event. #0 1 When LCDIF bit is set, this event causes an interrupt request. #1 LCDSTP LCD driver, charge pump, resistor bias network, and voltage regulator while in Stop mode. 8 1 read-write 0 Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode. #0 1 Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU goes into Stop mode. #1 LCDWAIT LCD driver, charge pump, resistor bias network, and voltage regulator stop while in Wait mode. 9 1 read-write 0 Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Wait mode. #0 1 Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU goes into Wait mode. #1 LCLK LCD clock prescaler 3 3 read-write RVEN Regulated voltage enable 31 1 read-write 0 Regulated voltage disabled. #0 1 Regulated voltage enabled. #1 RVTRIM Regulated voltage trim 24 4 read-write SOURCE LCD clock source select 6 1 read-write 0 Selects the default clock as the LCD clock source. #0 1 Selects the alternate clock as the LCD clock source. #1 VSUPPLY Voltage supply control 16 2 read-write 00 Drive VLL2 internally from VDD. #00 01 Drive VLL3 internally from VDD. #01 11 Drive VLL3 externally from VDD or drive VLL1 internally from VIREG. #11 PENH LCD pin enable register 0x34 32 read-write n 0x0 0x0 PEN LCD pin enable 0 32 read-write 0 LCD operation disabled on LCD_Pn. #0 1 LCD operation enabled on LCD_Pn. #1 PENL LCD pin enable register 0x20 32 read-write n 0x0 0x0 PEN LCD pin enable 0 32 read-write 0 LCD operation disabled on LCD_Pn. #0 1 LCD operation enabled on LCD_Pn. #1 WF0 LCD Waveform Register 0. LCD 0x20 8 read-write n 0x0 0x0 BPALCD0 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD0 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD0 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD0 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD0 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD0 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD0 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD0 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF1 LCD Waveform Register 1. 0x21 8 read-write n 0x0 0x0 BPALCD1 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD1 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD1 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD1 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD1 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD1 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD1 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD1 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF10 LCD Waveform Register 10. 0x2A 8 read-write n 0x0 0x0 BPALCD10 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD10 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD10 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD10 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD10 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD10 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD10 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD10 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF11 LCD Waveform Register 11. 0x2B 8 read-write n 0x0 0x0 BPALCD11 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD11 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD11 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD11 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD11 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD11 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD11 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD11 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF11TO8 LCD waveform register LCD 0x28 32 read-write n 0x0 0x0 WF10 no description available 16 8 read-write WF11 no description available 24 8 read-write WF8 no description available 0 8 read-write WF9 no description available 8 8 read-write WF12 LCD Waveform Register 12. LCD 0x2C 8 read-write n 0x0 0x0 BPALCD12 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD12 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD12 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD12 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD12 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD12 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD12 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD12 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF13 LCD Waveform Register 13. 0x2D 8 read-write n 0x0 0x0 BPALCD13 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD13 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD13 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD13 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD13 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD13 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD13 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD13 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF14 LCD Waveform Register 14. 0x2E 8 read-write n 0x0 0x0 BPALCD14 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD14 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD14 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD14 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD14 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD14 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD14 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD14 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF15 LCD Waveform Register 15. 0x2F 8 read-write n 0x0 0x0 BPALCD15 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD15 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD15 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD15 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD15 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD15 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD15 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD15 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF15TO12 LCD waveform register LCD 0x2C 32 read-write n 0x0 0x0 WF12 no description available 0 8 read-write WF13 no description available 8 8 read-write WF14 no description available 16 8 read-write WF15 no description available 24 8 read-write WF16 LCD Waveform Register 16. LCD 0x30 8 read-write n 0x0 0x0 BPALCD16 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD16 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD16 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD16 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD16 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD16 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD16 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD16 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF17 LCD Waveform Register 17. 0x31 8 read-write n 0x0 0x0 BPALCD17 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD17 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD17 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD17 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD17 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD17 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD17 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD17 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF18 LCD Waveform Register 18. 0x32 8 read-write n 0x0 0x0 BPALCD18 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD18 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD18 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD18 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD18 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD18 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD18 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD18 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF19 LCD Waveform Register 19. 0x33 8 read-write n 0x0 0x0 BPALCD19 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD19 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD19 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD19 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD19 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD19 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD19 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD19 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF19TO16 LCD waveform register LCD 0x30 32 read-write n 0x0 0x0 WF16 no description available 0 8 read-write WF17 no description available 8 8 read-write WF18 no description available 16 8 read-write WF19 no description available 24 8 read-write WF2 LCD Waveform Register 2. 0x22 8 read-write n 0x0 0x0 BPALCD2 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD2 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD2 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD2 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD2 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD2 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD2 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD2 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF20 LCD Waveform Register 20. LCD 0x34 8 read-write n 0x0 0x0 BPALCD20 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD20 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD20 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD20 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD20 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD20 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD20 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD20 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF21 LCD Waveform Register 21. 0x35 8 read-write n 0x0 0x0 BPALCD21 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD21 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD21 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD21 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD21 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD21 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD21 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD21 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF22 LCD Waveform Register 22. 0x36 8 read-write n 0x0 0x0 BPALCD22 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD22 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD22 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD22 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD22 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD22 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD22 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD22 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF23 LCD Waveform Register 23. 0x37 8 read-write n 0x0 0x0 BPALCD23 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD23 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD23 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD23 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD23 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD23 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD23 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD23 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF23TO20 LCD waveform register LCD 0x34 32 read-write n 0x0 0x0 WF20 no description available 0 8 read-write WF21 no description available 8 8 read-write WF22 no description available 16 8 read-write WF23 no description available 24 8 read-write WF24 LCD Waveform Register 24. LCD 0x38 8 read-write n 0x0 0x0 BPALCD24 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD24 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD24 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD24 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD24 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD24 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD24 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD24 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF25 LCD Waveform Register 25. 0x39 8 read-write n 0x0 0x0 BPALCD25 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD25 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD25 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD25 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD25 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD25 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD25 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD25 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF26 LCD Waveform Register 26. 0x3A 8 read-write n 0x0 0x0 BPALCD26 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD26 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD26 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD26 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD26 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD26 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD26 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD26 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF27 LCD Waveform Register 27. 0x3B 8 read-write n 0x0 0x0 BPALCD27 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD27 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD27 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD27 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD27 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD27 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD27 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD27 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF27TO24 LCD waveform register LCD 0x38 32 read-write n 0x0 0x0 WF24 no description available 0 8 read-write WF25 no description available 8 8 read-write WF26 no description available 16 8 read-write WF27 no description available 24 8 read-write WF28 LCD Waveform Register 28. LCD 0x3C 8 read-write n 0x0 0x0 BPALCD28 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD28 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD28 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD28 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD28 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD28 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD28 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD28 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF29 LCD Waveform Register 29. 0x3D 8 read-write n 0x0 0x0 BPALCD29 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD29 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD29 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD29 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD29 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD29 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD29 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD29 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF3 LCD Waveform Register 3. 0x23 8 read-write n 0x0 0x0 BPALCD3 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD3 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD3 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD3 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD3 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD3 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD3 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD3 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF30 LCD Waveform Register 30. 0x3E 8 read-write n 0x0 0x0 BPALCD30 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD30 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD30 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD30 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD30 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD30 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD30 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD30 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF31 LCD Waveform Register 31. 0x3F 8 read-write n 0x0 0x0 BPALCD31 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD31 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD31 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD31 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD31 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD31 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD31 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD31 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF31TO28 LCD waveform register LCD 0x3C 32 read-write n 0x0 0x0 WF28 no description available 0 8 read-write WF29 no description available 8 8 read-write WF30 no description available 16 8 read-write WF31 no description available 24 8 read-write WF32 LCD Waveform Register 32. LCD 0x40 8 read-write n 0x0 0x0 BPALCD32 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD32 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD32 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD32 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD32 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD32 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD32 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD32 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF33 LCD Waveform Register 33. 0x41 8 read-write n 0x0 0x0 BPALCD33 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD33 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD33 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD33 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD33 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD33 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD33 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD33 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF34 LCD Waveform Register 34. 0x42 8 read-write n 0x0 0x0 BPALCD34 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD34 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD34 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD34 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD34 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD34 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD34 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD34 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF35 LCD Waveform Register 35. 0x43 8 read-write n 0x0 0x0 BPALCD35 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD35 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD35 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD35 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD35 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD35 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD35 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD35 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF35TO32 LCD waveform register LCD 0x40 32 read-write n 0x0 0x0 WF32 no description available 0 8 read-write WF33 no description available 8 8 read-write WF34 no description available 16 8 read-write WF35 no description available 24 8 read-write WF36 LCD Waveform Register 36. LCD 0x44 8 read-write n 0x0 0x0 BPALCD36 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD36 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD36 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD36 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD36 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD36 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD36 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD36 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF37 LCD Waveform Register 37. 0x45 8 read-write n 0x0 0x0 BPALCD37 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD37 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD37 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD37 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD37 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD37 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD37 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD37 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF38 LCD Waveform Register 38. 0x46 8 read-write n 0x0 0x0 BPALCD38 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD38 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD38 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD38 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD38 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD38 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD38 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD38 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF39 LCD Waveform Register 39. 0x47 8 read-write n 0x0 0x0 BPALCD39 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD39 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD39 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD39 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD39 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD39 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD39 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD39 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF39TO36 LCD waveform register LCD 0x44 32 read-write n 0x0 0x0 WF36 no description available 0 8 read-write WF37 no description available 8 8 read-write WF38 no description available 16 8 read-write WF39 no description available 24 8 read-write WF3TO0 LCD waveform register LCD 0x20 32 read-write n 0x0 0x0 WF0 no description available 0 8 read-write WF1 no description available 8 8 read-write WF2 no description available 16 8 read-write WF3 no description available 24 8 read-write WF4 LCD Waveform Register 4. LCD 0x24 8 read-write n 0x0 0x0 BPALCD4 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD4 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD4 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD4 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD4 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD4 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD4 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD4 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF40 LCD Waveform Register 40. LCD 0x48 8 read-write n 0x0 0x0 BPALCD40 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD40 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD40 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD40 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD40 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD40 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD40 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD40 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF41 LCD Waveform Register 41. 0x49 8 read-write n 0x0 0x0 BPALCD41 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD41 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD41 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD41 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD41 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD41 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD41 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD41 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF42 LCD Waveform Register 42. 0x4A 8 read-write n 0x0 0x0 BPALCD42 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD42 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD42 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD42 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD42 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD42 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD42 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD42 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF43 LCD Waveform Register 43. 0x4B 8 read-write n 0x0 0x0 BPALCD43 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD43 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD43 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD43 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD43 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD43 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD43 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD43 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF43TO40 LCD waveform register LCD 0x48 32 read-write n 0x0 0x0 WF40 no description available 0 8 read-write WF41 no description available 8 8 read-write WF42 no description available 16 8 read-write WF43 no description available 24 8 read-write WF44 LCD Waveform Register 44. LCD 0x4C 8 read-write n 0x0 0x0 BPALCD44 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD44 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD44 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD44 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD44 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD44 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD44 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD44 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF45 LCD Waveform Register 45. 0x4D 8 read-write n 0x0 0x0 BPALCD45 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD45 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD45 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD45 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD45 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD45 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD45 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD45 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF46 LCD Waveform Register 46. 0x4E 8 read-write n 0x0 0x0 BPALCD46 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD46 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD46 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD46 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD46 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD46 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD46 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD46 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF47 LCD Waveform Register 47. 0x4F 8 read-write n 0x0 0x0 BPALCD47 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD47 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD47 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD47 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD47 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD47 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD47 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD47 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF47TO44 LCD waveform register LCD 0x4C 32 read-write n 0x0 0x0 WF44 no description available 0 8 read-write WF45 no description available 8 8 read-write WF46 no description available 16 8 read-write WF47 no description available 24 8 read-write WF48 LCD Waveform Register 48. LCD 0x50 8 read-write n 0x0 0x0 BPALCD48 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD48 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD48 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD48 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD48 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD48 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD48 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD48 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF49 LCD Waveform Register 49. 0x51 8 read-write n 0x0 0x0 BPALCD49 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD49 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD49 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD49 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD49 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD49 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD49 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD49 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF5 LCD Waveform Register 5. 0x25 8 read-write n 0x0 0x0 BPALCD5 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD5 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD5 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD5 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD5 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD5 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD5 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD5 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF50 LCD Waveform Register 50. 0x52 8 read-write n 0x0 0x0 BPALCD50 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD50 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD50 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD50 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD50 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD50 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD50 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD50 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF51 LCD Waveform Register 51. 0x53 8 read-write n 0x0 0x0 BPALCD51 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD51 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD51 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD51 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD51 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD51 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD51 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD51 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF51TO48 LCD waveform register LCD 0x50 32 read-write n 0x0 0x0 WF48 no description available 0 8 read-write WF49 no description available 8 8 read-write WF50 no description available 16 8 read-write WF51 no description available 24 8 read-write WF52 LCD Waveform Register 52. LCD 0x54 8 read-write n 0x0 0x0 BPALCD52 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD52 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD52 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD52 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD52 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD52 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD52 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD52 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF53 LCD Waveform Register 53. 0x55 8 read-write n 0x0 0x0 BPALCD53 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD53 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD53 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD53 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD53 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD53 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD53 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD53 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF54 LCD Waveform Register 54. 0x56 8 read-write n 0x0 0x0 BPALCD54 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD54 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD54 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD54 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD54 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD54 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD54 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD54 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF55 LCD Waveform Register 55. 0x57 8 read-write n 0x0 0x0 BPALCD55 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD55 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD55 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD55 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD55 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD55 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD55 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD55 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF55TO52 LCD waveform register LCD 0x54 32 read-write n 0x0 0x0 WF52 no description available 0 8 read-write WF53 no description available 8 8 read-write WF54 no description available 16 8 read-write WF55 no description available 24 8 read-write WF56 LCD Waveform Register 56. LCD 0x58 8 read-write n 0x0 0x0 BPALCD56 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD56 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD56 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD56 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD56 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD56 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD56 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD56 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF57 LCD Waveform Register 57. 0x59 8 read-write n 0x0 0x0 BPALCD57 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD57 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD57 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD57 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD57 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD57 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD57 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD57 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF58 LCD Waveform Register 58. 0x5A 8 read-write n 0x0 0x0 BPALCD58 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD58 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD58 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD58 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD58 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD58 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD58 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD58 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF59 LCD Waveform Register 59. 0x5B 8 read-write n 0x0 0x0 BPALCD59 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD59 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD59 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD59 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD59 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD59 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD59 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD59 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF59TO56 LCD waveform register LCD 0x58 32 read-write n 0x0 0x0 WF56 no description available 0 8 read-write WF57 no description available 8 8 read-write WF58 no description available 16 8 read-write WF59 no description available 24 8 read-write WF6 LCD Waveform Register 6. 0x26 8 read-write n 0x0 0x0 BPALCD6 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD6 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD6 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD6 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD6 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD6 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD6 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD6 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF60 LCD Waveform Register 60. LCD 0x5C 8 read-write n 0x0 0x0 BPALCD60 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD60 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD60 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD60 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD60 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD60 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD60 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD60 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF61 LCD Waveform Register 61. 0x5D 8 read-write n 0x0 0x0 BPALCD61 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD61 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD61 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD61 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD61 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD61 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD61 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD61 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF62 LCD Waveform Register 62. 0x5E 8 read-write n 0x0 0x0 BPALCD62 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD62 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD62 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD62 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD62 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD62 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD62 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD62 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF63 LCD Waveform Register 63. 0x5F 8 read-write n 0x0 0x0 BPALCD63 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD63 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD63 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD63 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD63 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD63 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD63 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD63 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF63TO60 LCD waveform register LCD 0x5C 32 read-write n 0x0 0x0 WF60 no description available 0 8 read-write WF61 no description available 8 8 read-write WF62 no description available 16 8 read-write WF63 no description available 24 8 read-write WF7 LCD Waveform Register 7. 0x27 8 read-write n 0x0 0x0 BPALCD7 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD7 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD7 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD7 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD7 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD7 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD7 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD7 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF7TO4 LCD waveform register LCD 0x24 32 read-write n 0x0 0x0 WF4 no description available 0 8 read-write WF5 no description available 8 8 read-write WF6 no description available 16 8 read-write WF7 no description available 24 8 read-write WF8 LCD Waveform Register 8. LCD 0x28 8 read-write n 0x0 0x0 BPALCD8 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD8 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD8 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD8 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD8 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD8 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD8 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD8 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 WF9 LCD Waveform Register 9. 0x29 8 read-write n 0x0 0x0 BPALCD9 no description available 0 1 read-write 0 LCD segment off or LCD backplane inactive for phase A #0 1 LCD segment on or LCD backplane active for phase A #1 BPBLCD9 no description available 1 1 read-write 0 LCD segment off or LCD backplane inactive for phase B #0 1 LCD segment on or LCD backplane active for phase B #1 BPCLCD9 no description available 2 1 read-write 0 LCD segment off or LCD backplane inactive for phase C #0 1 LCD segment on or LCD backplane active for phase C #1 BPDLCD9 no description available 3 1 read-write 0 LCD segment off or LCD backplane inactive for phase D #0 1 LCD segment on or LCD backplane active for phase D #1 BPELCD9 no description available 4 1 read-write 0 LCD segment off or LCD backplane inactive for phase E #0 1 LCD segment on or LCD backplane active for phase E #1 BPFLCD9 no description available 5 1 read-write 0 LCD segment off or LCD backplane inactive for phase F #0 1 LCD segment on or LCD backplane active for phase F #1 BPGLCD9 no description available 6 1 read-write 0 LCD segment off or LCD backplane inactive for phase G #0 1 LCD segment on or LCD backplane active for phase G #1 BPHLCD9 no description available 7 1 read-write 0 LCD segment off or LCD backplane inactive for phase H #0 1 LCD segment on or LCD backplane active for phase H #1 LLWU Low-leakage wake-up module LLWU 0x0 0x0 0x9 registers n LLW 21 CS LLWU Control and Status Register 0x8 8 read-write n 0x0 0x0 ACKISO Acknowledge Isolation 7 1 read-write 0 Peripherals and I/O pads are in normal run state #0 1 Certain peripherals and I/O pads are in an isolated and latched state #1 FLTEP Digital Filter on External Pin 1 1 read-write 0 Filter not enabled #0 1 Filter enabled #1 FLTR Digital Filter on RESET Pin 0 1 read-write 0 Filter not enabled #0 1 Filter enabled #1 F1 LLWU Flag 1 Register 0x5 8 read-write n 0x0 0x0 WUF0 Wakeup Flag for LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P0 input was a source of wakeup from LLS or VLLS mode #1 WUF1 Wakeup Flag for LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P1 input was a source of wakeup from LLS or VLLS mode #1 WUF2 Wakeup Flag for LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P2 input was a source of wakeup from LLS or VLLS mode #1 WUF3 Wakeup Flag for LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P3 input was a source of wakeup from LLS or VLLS mode #1 WUF4 Wakeup Flag for LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P4 input was a source of wakeup from LLS or VLLS mode #1 WUF5 Wakeup Flag for LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P5 input was a source of wakeup from LLS or VLLS mode #1 WUF6 Wakeup Flag for LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P6 input was a source of wakeup from LLS or VLLS mode #1 WUF7 Wakeup Flag for LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P7 input was a source of wakeup from LLS or VLLS mode #1 F2 LLWU Flag 2 Register 0x6 8 read-write n 0x0 0x0 WUF10 Wakeup Flag for LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P10 input was a source of wakeup from LLS or VLLS mode #1 WUF11 Wakeup Flag for LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P11 input was a source of wakeup from LLS or VLLS mode #1 WUF12 Wakeup Flag for LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P12 input was a source of wakeup from LLS or VLLS mode #1 WUF13 Wakeup Flag for LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P13 input was a source of wakeup from LLS or VLLS mode #1 WUF14 Wakeup Flag for LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P14 input was a source of wakeup from LLS or VLLS mode #1 WUF15 Wakeup Flag for LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P15 input was a source of wakeup from LLS or VLLS mode #1 WUF8 Wakeup Flag for LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P8 input was a source of wakeup from LLS or VLLS mode #1 WUF9 Wakeup Flag for LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a source of wakeup from LLS or VLLS mode #0 1 LLWU_P9 input was a source of wakeup from LLS or VLLS mode #1 F3 LLWU Flag 3 Register 0x7 8 read-write n 0x0 0x0 MWUF0 Wakeup flag for module 0 0 1 read-only 0 Module 0 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 0 input was a source of wakeup from LLS or VLLS mode #1 MWUF1 Wakeup flag for module 1 1 1 read-only 0 Module 1 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 1 input was a source of wakeup from LLS or VLLS mode #1 MWUF2 Wakeup flag for module 2 2 1 read-only 0 Module 2 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 2 input was a source of wakeup from LLS or VLLS mode #1 MWUF3 Wakeup flag for module 3 3 1 read-only 0 Module 3 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 3 input was a source of wakeup from LLS or VLLS mode #1 MWUF4 Wakeup flag for module 4 4 1 read-only 0 Module 4 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 4 input was a source of wakeup from LLS or VLLS mode #1 MWUF5 Wakeup flag for module 5 5 1 read-only 0 Module 5 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 5 input was a source of wakeup from LLS or VLLS mode #1 MWUF6 Wakeup flag for module 6 6 1 read-only 0 Module 6 input was not a source of wakeup from LLS or VLLS mode #0 1 Module 6 input was a source of wakeup from LLS or VLLS mode #1 MWUF7 Wakeup flag for module 7 (Error Detect) 7 1 read-write 0 Module 7 (Error Detect) input was not a source of wakeup from LLS or VLLS mode #0 1 Module 7 (Error Detect) input was a source of wakeup from LLS or VLLS mode #1 ME LLWU Module Enable Register 0x4 8 read-write n 0x0 0x0 WUME0 Wakeup Module Enable for Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable for Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable for Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable for Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable for Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable for Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable for Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 PE1 LLWU Pin Enable 1 Register 0x0 8 read-write n 0x0 0x0 WUPE0 Wakeup Pin Enable for LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable for LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable for LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable for LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 Register 0x1 8 read-write n 0x0 0x0 WUPE4 Wakeup Pin Enable for LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable for LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable for LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable for LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 Register 0x2 8 read-write n 0x0 0x0 WUPE10 Wakeup Pin Enable for LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable for LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE8 Wakeup Pin Enable for LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable for LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 Register 0x3 8 read-write n 0x0 0x0 WUPE12 Wakeup Pin Enable for LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable for LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable for LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable for LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 LPTMR0 Low Power Timer LPTMR0 0x0 0x0 0x10 registers n LPTimer 85 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 16 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write 0 LPTMR Counter Register has not equaled the LPTMR Compare Register and incremented #0 1 LPTMR Counter Register has equaled the LPTMR Compare Register and incremented #1 TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TFC Timer Free Running Counter 2 1 read-write 0 LPTMR Counter Register is reset whenever the Timer Compare Flag is set. #0 1 LPTMR Counter Register is reset on overflow. #1 TIE Timer Interrupt Enable 6 1 read-write 0 Timer Interrupt Disabled. #0 1 Timer Interrupt Enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active high, and LPTMR Counter Register will increment on the rising edge. #0 1 Pulse Counter input source is active low, and LPTMR Counter Register will increment on the falling edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/Glitch Filter is enabled. #0 1 Prescaler/Glitch Filter is bypassed. #1 PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected #00 01 Prescaler/glitch filter clock 1 selected #01 10 Prescaler/glitch filter clock 2 selected #10 11 Prescaler/glitch filter clock 3 selected #11 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; Glitch Filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; Glitch Filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; Glitch Filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; Glitch Filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; Glitch Filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; Glitch Filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; Glitch Filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; Glitch Filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; Glitch Filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; Glitch Filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; Glitch Filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; Glitch Filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; Glitch Filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16384; Glitch Filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32768; Glitch Filter recognizes change on input pin after 16384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65536; Glitch Filter recognizes change on input pin after 32768 rising clock edges. #1111 MC Mode Controller MC 0x0 0x0 0x4 registers n PMCTRL Power Mode Control Register 0x3 8 read-write n 0x0 0x0 LPLLSM Low Power, Low Leakage Stop Mode 0 3 read-write 000 Normal stop #000 010 Very low power stop (VLPS) #010 011 Low leakage stop (LLS) #011 101 Very low leakage stop 3 (VLLS3) #101 110 Very low leakage stop 2 (VLLS2) #110 111 Very low leakage stop 1 (VLLS1) #111 LPWUI Low Power Wake Up on Interrupt 7 1 read-write 0 The voltage regulator remains in stop regulation on an interrupt #0 1 The voltage regulator exits stop regulation on an interrupt #1 RUNM Run Mode Enable 5 2 read-write 00 Normal run mode #00 10 Very low power run mode #10 PMPROT Power Mode Protection Register 0x2 8 read-write n 0x0 0x0 ALLS Allow low leakage stop mode 4 1 read-write 0 LLS is not allowed #0 1 LLS is allowed #1 AVLLS1 Allow very low leakage stop 1 mode 0 1 read-write 0 VLLS1 is not allowed #0 1 VLLS1 is allowed #1 AVLLS2 Allow very low leakage stop 2 mode 1 1 read-write 0 VLLS2 is not allowed #0 1 VLLS2 is allowed #1 AVLLS3 Allow Very Low Leakage Stop 3 Mode 2 1 read-write 0 VLLS3 is not allowed #0 1 VLLS3 is allowed #1 AVLP Allow very low power modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed #0 1 VLPR, VLPW, and VLPS are allowed #1 SRSH System Reset Status Register High 0x0 8 read-only n 0x0 0x0 JTAG JTAG generated reset 0 1 read-only 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 LOCKUP Core Lock-up 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 SRSL System Reset Status Register Low 0x1 8 read-only n 0x0 0x0 COP Computer Operating Properly (COP) Watchdog 5 1 read-only 0 Reset not caused by COP timeout #0 1 Reset caused by COP timeout #1 LOC Loss-of-clock reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LVD Low-voltage detect reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 PIN External reset pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-on reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 WAKEUP Low-leakage wakeup reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 MCG Multipurpose Clock Generator module MCG 0x0 0x0 0xC registers n ATC MCG Auto Trim Control Register 0x8 8 read-write n 0x0 0x0 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATMF Automatic Trim machine Fail Flag 5 1 read-only 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write n 0x0 0x0 ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write n 0x0 0x0 ATCVL ATM Compare Value Low 0 8 read-write C1 MCG Control 1 Register 0x0 8 read-write n 0x0 0x0 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved, defaults to 00. #11 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is Reserved . #110 111 If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is Reserved . #111 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 C2 MCG Control 2 Register 0x1 8 read-write n 0x0 0x0 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LP Low Power Select 1 1 read-write 0 FLL (or PLL) is not disabled in bypass modes. #0 1 FLL (or PLL) is disabled in bypass modes (lower power) #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 C3 MCG Control 3 Register 0x2 8 read-write n 0x0 0x0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write n 0x0 0x0 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write C5 MCG Control 5 Register 0x4 8 read-write n 0x0 0x0 PLLCLKEN PLL Clock Enable 6 1 read-write 0 MCGPLLCLK is inactive. #0 1 MCGPLLCLK is active. #1 PLLSTEN PLL Stop Enable 5 1 read-write 0 MCGPLLCLK is disabled in any of the Stop modes. #0 1 MCGPLLCLK is enabled if system is in Normal Stop mode. #1 PRDIV PLL External Reference Divider 0 5 read-write C6 MCG Control 6 Register 0x5 8 read-write n 0x0 0x0 CME Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled. #0 1 Generate a reset request on loss of external clock. #1 LOLIE Loss of Lock Interrrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock. #0 1 Generate an interrupt request on loss of lock. #1 PLLS PLL Select 6 1 read-write 0 FLL is selected. #0 1 PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz prior to setting the PLLS bit). #1 VDIV VCO Divider 0 5 read-write S MCG Status Register 0x6 8 read-write n 0x0 0x0 CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Output of the PLL is selected. #11 IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (2 MHz IRC). #1 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 LOCK Lock Status 6 1 read-only 0 PLL is currently unlocked. #0 1 PLL is currently locked. #1 LOLS Loss of Lock Status 7 1 read-write 0 PLL has not lost lock since LOLS was last cleared. #0 1 PLL has lost lock since LOLS was last cleared. #1 OSCINIT OSC Initialization 1 1 read-only PLLST PLL Select Status 5 1 read-only 0 Source of PLLS clock is FLL clock. #0 1 Source of PLLS clock is PLL clock. #1 MCM Core Platform Miscellaneous Control Module MCM 0x0 0x8 0x18 registers n ETBCC ETB counter control register 0x14 32 read-write n 0x0 0x0 CNTEN Counter enable 0 1 read-write 0 ETB counter disabled #0 1 ETB counter enabled #1 ETDIS ETM-to-TPIU disable 4 1 read-write 0 ETM-to-TPIU trace path enabled #0 1 ETM-to-TPIU trace path disabled #1 ITDIS ITM-to-TPIU disable 5 1 read-write 0 ITM-to-TPIU trace path enabled #0 1 ITM-to-TPIU trace path disabled #1 RLRQ Reload request 3 1 read-write 0 No effect #0 1 Clears pending debug halt, NMI, or IRQ interrupt requests #1 RSPT Response type 1 2 read-write 00 No response when the ETB count expires #00 01 Generate a normal interrupt when the ETB count expires #01 10 Generate an NMI when the ETB count expires #10 11 Generate a debug halt when the ETB count expires #11 ETBCNT ETB counter value register 0x1C 32 read-only n 0x0 0x0 COUNTER Byte count counter value 0 11 read-only ETBRL ETB reload register 0x18 32 read-write n 0x0 0x0 RELOAD Byte count reload value 0 11 read-write ISR Interrupt status register 0x10 32 read-write n 0x0 0x0 IRQ Normal interrupt pending 1 1 read-write 0 No pending interrupt #0 1 Due to the ETB counter expiring, a normal interrupt is pending #1 NMI Non-maskable interrupt pending 2 1 read-write 0 No pending NMI #0 1 Due to the ETB counter expiring, an NMI is pending #1 PLAMC Crossbar switch (AXBS) master configuration 0xA 16 read-only n 0x0 0x0 AMC Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLASC Crossbar switch (AXBS) slave configuration 0x8 16 read-only n 0x0 0x0 ASC Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 SRAMAP SRAM arbitration and protection 0xC 32 read-write n 0x0 0x0 SRAMLAP SRAM_L arbitration priority 28 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMLWP SRAM_L write protect 30 1 read-write SRAMUAP SRAM_U arbitration priority 24 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMUWP SRAM_U write protect 26 1 read-write MPU Memory protection unit MPU 0x0 0x0 0x830 registers n CESR Control/Error Status Register 0x0 32 read-write n 0x0 0x0 HRL Hardware revision level 16 4 read-only NRGD Number of region descriptors 8 4 read-only 0000 8 region descriptors #0000 0001 12 region descriptors #0001 0010 16 region descriptors #0010 NSP Number of slave ports 12 4 read-only SPERR Slave port n error 27 5 read-write 0 No error has occurred for slave port n. #0 1 An error has occurred for slave port n. #1 VLD Valid (global enable/disable for the MPU) 0 1 read-write 0 MPU is disabled. All accesses from all bus masters are allowed. #0 1 MPU is enabled #1 EAR0 Error Address Register, Slave Port n 0x20 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR1 Error Address Register, Slave Port n 0x38 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR2 Error Address Register, Slave Port n 0x58 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR3 Error Address Register, Slave Port n 0x80 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR4 Error Address Register, Slave Port n 0xB0 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EDR0 Error Detail Register, Slave Port n 0x28 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR1 Error Detail Register, Slave Port n 0x44 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR2 Error Detail Register, Slave Port n 0x68 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR3 Error Detail Register, Slave Port n 0x94 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR4 Error Detail Register, Slave Port n 0xC8 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 RGD0_WORD0 Region Descriptor n, Word 0 0x800 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD0_WORD1 Region Descriptor n, Word 1 0x808 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD0_WORD2 Region Descriptor n, Word 2 0x810 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD0_WORD3 Region Descriptor n, Word 3 0x818 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD10_WORD0 Region Descriptor n, Word 0 0x3370 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD10_WORD1 Region Descriptor n, Word 1 0x33A0 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD10_WORD2 Region Descriptor n, Word 2 0x33D0 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD10_WORD3 Region Descriptor n, Word 3 0x3400 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD11_WORD0 Region Descriptor n, Word 0 0x3820 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD11_WORD1 Region Descriptor n, Word 1 0x3854 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD11_WORD2 Region Descriptor n, Word 2 0x3888 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD11_WORD3 Region Descriptor n, Word 3 0x38BC 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD1_WORD0 Region Descriptor n, Word 0 0xC10 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD1_WORD1 Region Descriptor n, Word 1 0xC1C 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD1_WORD2 Region Descriptor n, Word 2 0xC28 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD1_WORD3 Region Descriptor n, Word 3 0xC34 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD2_WORD0 Region Descriptor n, Word 0 0x1030 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD2_WORD1 Region Descriptor n, Word 1 0x1040 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD2_WORD2 Region Descriptor n, Word 2 0x1050 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD2_WORD3 Region Descriptor n, Word 3 0x1060 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD3_WORD0 Region Descriptor n, Word 0 0x1460 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD3_WORD1 Region Descriptor n, Word 1 0x1474 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD3_WORD2 Region Descriptor n, Word 2 0x1488 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD3_WORD3 Region Descriptor n, Word 3 0x149C 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD4_WORD0 Region Descriptor n, Word 0 0x18A0 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD4_WORD1 Region Descriptor n, Word 1 0x18B8 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD4_WORD2 Region Descriptor n, Word 2 0x18D0 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD4_WORD3 Region Descriptor n, Word 3 0x18E8 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD5_WORD0 Region Descriptor n, Word 0 0x1CF0 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD5_WORD1 Region Descriptor n, Word 1 0x1D0C 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD5_WORD2 Region Descriptor n, Word 2 0x1D28 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD5_WORD3 Region Descriptor n, Word 3 0x1D44 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD6_WORD0 Region Descriptor n, Word 0 0x2150 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD6_WORD1 Region Descriptor n, Word 1 0x2170 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD6_WORD2 Region Descriptor n, Word 2 0x2190 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD6_WORD3 Region Descriptor n, Word 3 0x21B0 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD7_WORD0 Region Descriptor n, Word 0 0x25C0 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD7_WORD1 Region Descriptor n, Word 1 0x25E4 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD7_WORD2 Region Descriptor n, Word 2 0x2608 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD7_WORD3 Region Descriptor n, Word 3 0x262C 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD8_WORD0 Region Descriptor n, Word 0 0x2A40 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD8_WORD1 Region Descriptor n, Word 1 0x2A68 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD8_WORD2 Region Descriptor n, Word 2 0x2A90 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD8_WORD3 Region Descriptor n, Word 3 0x2AB8 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD9_WORD0 Region Descriptor n, Word 0 0x2ED0 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD9_WORD1 Region Descriptor n, Word 1 0x2EFC 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD9_WORD2 Region Descriptor n, Word 2 0x2F28 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD9_WORD3 Region Descriptor n, Word 3 0x2F54 32 read-write n 0x0 0x0 VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGDAAC0 Region Descriptor Alternate Access Control n 0x1000 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC1 Region Descriptor Alternate Access Control n 0x1804 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC10 Region Descriptor Alternate Access Control n 0x60DC 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC11 Region Descriptor Alternate Access Control n 0x6908 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC2 Region Descriptor Alternate Access Control n 0x200C 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC3 Region Descriptor Alternate Access Control n 0x2818 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC4 Region Descriptor Alternate Access Control n 0x3028 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC5 Region Descriptor Alternate Access Control n 0x383C 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC6 Region Descriptor Alternate Access Control n 0x4054 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC7 Region Descriptor Alternate Access Control n 0x4870 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC8 Region Descriptor Alternate Access Control n 0x5090 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC9 Region Descriptor Alternate Access Control n 0x58B4 32 read-write n 0x0 0x0 M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0xE04 registers n NVICIABR0 Interrupt Active bit Register n 0x200 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICIABR1 Interrupt Active bit Register n 0x204 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICIABR2 Interrupt Active bit Register n 0x208 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICIABR3 Interrupt Active bit Register n 0x20C 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICICER0 Interrupt Clear Enable Register n 0x80 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER1 Interrupt Clear Enable Register n 0x84 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER2 Interrupt Clear Enable Register n 0x88 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER3 Interrupt Clear Enable Register n 0x8C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICPR0 Interrupt Clear Pending Register n 0x180 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR1 Interrupt Clear Pending Register n 0x184 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR2 Interrupt Clear Pending Register n 0x188 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICIP0 Interrupt Priority Register n 0x300 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 read-write NVICIP1 Interrupt Priority Register n 0x301 8 read-write n 0x0 0x0 PRI1 Priority of interrupt 1 0 8 read-write NVICIP10 Interrupt Priority Register n 0x30A 8 read-write n 0x0 0x0 PRI10 Priority of interrupt 10 0 8 read-write NVICIP100 Interrupt Priority Register n 0x364 8 read-write n 0x0 0x0 PRI100 Priority of interrupt 100 0 8 read-write NVICIP101 Interrupt Priority Register n 0x365 8 read-write n 0x0 0x0 PRI101 Priority of interrupt 101 0 8 read-write NVICIP102 Interrupt Priority Register n 0x366 8 read-write n 0x0 0x0 PRI102 Priority of interrupt 102 0 8 read-write NVICIP103 Interrupt Priority Register n 0x367 8 read-write n 0x0 0x0 PRI103 Priority of interrupt 103 0 8 read-write NVICIP104 Interrupt Priority Register n 0x368 8 read-write n 0x0 0x0 PRI104 Priority of interrupt 104 0 8 read-write NVICIP105 Interrupt Priority Register n 0x369 8 read-write n 0x0 0x0 PRI105 Priority of interrupt 105 0 8 read-write NVICIP11 Interrupt Priority Register n 0x30B 8 read-write n 0x0 0x0 PRI11 Priority of interrupt 11 0 8 read-write NVICIP12 Interrupt Priority Register n 0x30C 8 read-write n 0x0 0x0 PRI12 Priority of interrupt 12 0 8 read-write NVICIP13 Interrupt Priority Register n 0x30D 8 read-write n 0x0 0x0 PRI13 Priority of interrupt 13 0 8 read-write NVICIP14 Interrupt Priority Register n 0x30E 8 read-write n 0x0 0x0 PRI14 Priority of interrupt 14 0 8 read-write NVICIP15 Interrupt Priority Register n 0x30F 8 read-write n 0x0 0x0 PRI15 Priority of interrupt 15 0 8 read-write NVICIP16 Interrupt Priority Register n 0x310 8 read-write n 0x0 0x0 PRI16 Priority of interrupt 16 0 8 read-write NVICIP17 Interrupt Priority Register n 0x311 8 read-write n 0x0 0x0 PRI17 Priority of interrupt 17 0 8 read-write NVICIP18 Interrupt Priority Register n 0x312 8 read-write n 0x0 0x0 PRI18 Priority of interrupt 18 0 8 read-write NVICIP19 Interrupt Priority Register n 0x313 8 read-write n 0x0 0x0 PRI19 Priority of interrupt 19 0 8 read-write NVICIP2 Interrupt Priority Register n 0x302 8 read-write n 0x0 0x0 PRI2 Priority of interrupt 2 0 8 read-write NVICIP20 Interrupt Priority Register n 0x314 8 read-write n 0x0 0x0 PRI20 Priority of interrupt 20 0 8 read-write NVICIP21 Interrupt Priority Register n 0x315 8 read-write n 0x0 0x0 PRI21 Priority of interrupt 21 0 8 read-write NVICIP22 Interrupt Priority Register n 0x316 8 read-write n 0x0 0x0 PRI22 Priority of interrupt 22 0 8 read-write NVICIP23 Interrupt Priority Register n 0x317 8 read-write n 0x0 0x0 PRI23 Priority of interrupt 23 0 8 read-write NVICIP24 Interrupt Priority Register n 0x318 8 read-write n 0x0 0x0 PRI24 Priority of interrupt 24 0 8 read-write NVICIP25 Interrupt Priority Register n 0x319 8 read-write n 0x0 0x0 PRI25 Priority of interrupt 25 0 8 read-write NVICIP26 Interrupt Priority Register n 0x31A 8 read-write n 0x0 0x0 PRI26 Priority of interrupt 26 0 8 read-write NVICIP27 Interrupt Priority Register n 0x31B 8 read-write n 0x0 0x0 PRI27 Priority of interrupt 27 0 8 read-write NVICIP28 Interrupt Priority Register n 0x31C 8 read-write n 0x0 0x0 PRI28 Priority of interrupt 28 0 8 read-write NVICIP29 Interrupt Priority Register n 0x31D 8 read-write n 0x0 0x0 PRI29 Priority of interrupt 29 0 8 read-write NVICIP3 Interrupt Priority Register n 0x303 8 read-write n 0x0 0x0 PRI3 Priority of interrupt 3 0 8 read-write NVICIP30 Interrupt Priority Register n 0x31E 8 read-write n 0x0 0x0 PRI30 Priority of interrupt 30 0 8 read-write NVICIP31 Interrupt Priority Register n 0x31F 8 read-write n 0x0 0x0 PRI31 Priority of interrupt 31 0 8 read-write NVICIP32 Interrupt Priority Register n 0x320 8 read-write n 0x0 0x0 PRI32 Priority of interrupt 32 0 8 read-write NVICIP33 Interrupt Priority Register n 0x321 8 read-write n 0x0 0x0 PRI33 Priority of interrupt 33 0 8 read-write NVICIP34 Interrupt Priority Register n 0x322 8 read-write n 0x0 0x0 PRI34 Priority of interrupt 34 0 8 read-write NVICIP35 Interrupt Priority Register n 0x323 8 read-write n 0x0 0x0 PRI35 Priority of interrupt 35 0 8 read-write NVICIP36 Interrupt Priority Register n 0x324 8 read-write n 0x0 0x0 PRI36 Priority of interrupt 36 0 8 read-write NVICIP37 Interrupt Priority Register n 0x325 8 read-write n 0x0 0x0 PRI37 Priority of interrupt 37 0 8 read-write NVICIP38 Interrupt Priority Register n 0x326 8 read-write n 0x0 0x0 PRI38 Priority of interrupt 38 0 8 read-write NVICIP39 Interrupt Priority Register n 0x327 8 read-write n 0x0 0x0 PRI39 Priority of interrupt 39 0 8 read-write NVICIP4 Interrupt Priority Register n 0x304 8 read-write n 0x0 0x0 PRI4 Priority of interrupt 4 0 8 read-write NVICIP40 Interrupt Priority Register n 0x328 8 read-write n 0x0 0x0 PRI40 Priority of interrupt 40 0 8 read-write NVICIP41 Interrupt Priority Register n 0x329 8 read-write n 0x0 0x0 PRI41 Priority of interrupt 41 0 8 read-write NVICIP42 Interrupt Priority Register n 0x32A 8 read-write n 0x0 0x0 PRI42 Priority of interrupt 42 0 8 read-write NVICIP43 Interrupt Priority Register n 0x32B 8 read-write n 0x0 0x0 PRI43 Priority of interrupt 43 0 8 read-write NVICIP44 Interrupt Priority Register n 0x32C 8 read-write n 0x0 0x0 PRI44 Priority of interrupt 44 0 8 read-write NVICIP45 Interrupt Priority Register n 0x32D 8 read-write n 0x0 0x0 PRI45 Priority of interrupt 45 0 8 read-write NVICIP46 Interrupt Priority Register n 0x32E 8 read-write n 0x0 0x0 PRI46 Priority of interrupt 46 0 8 read-write NVICIP47 Interrupt Priority Register n 0x32F 8 read-write n 0x0 0x0 PRI47 Priority of interrupt 47 0 8 read-write NVICIP48 Interrupt Priority Register n 0x330 8 read-write n 0x0 0x0 PRI48 Priority of interrupt 48 0 8 read-write NVICIP49 Interrupt Priority Register n 0x331 8 read-write n 0x0 0x0 PRI49 Priority of interrupt 49 0 8 read-write NVICIP5 Interrupt Priority Register n 0x305 8 read-write n 0x0 0x0 PRI5 Priority of interrupt 5 0 8 read-write NVICIP50 Interrupt Priority Register n 0x332 8 read-write n 0x0 0x0 PRI50 Priority of interrupt 50 0 8 read-write NVICIP51 Interrupt Priority Register n 0x333 8 read-write n 0x0 0x0 PRI51 Priority of interrupt 51 0 8 read-write NVICIP52 Interrupt Priority Register n 0x334 8 read-write n 0x0 0x0 PRI52 Priority of interrupt 52 0 8 read-write NVICIP53 Interrupt Priority Register n 0x335 8 read-write n 0x0 0x0 PRI53 Priority of interrupt 53 0 8 read-write NVICIP54 Interrupt Priority Register n 0x336 8 read-write n 0x0 0x0 PRI54 Priority of interrupt 54 0 8 read-write NVICIP55 Interrupt Priority Register n 0x337 8 read-write n 0x0 0x0 PRI55 Priority of interrupt 55 0 8 read-write NVICIP56 Interrupt Priority Register n 0x338 8 read-write n 0x0 0x0 PRI56 Priority of interrupt 56 0 8 read-write NVICIP57 Interrupt Priority Register n 0x339 8 read-write n 0x0 0x0 PRI57 Priority of interrupt 57 0 8 read-write NVICIP58 Interrupt Priority Register n 0x33A 8 read-write n 0x0 0x0 PRI58 Priority of interrupt 58 0 8 read-write NVICIP59 Interrupt Priority Register n 0x33B 8 read-write n 0x0 0x0 PRI59 Priority of interrupt 59 0 8 read-write NVICIP6 Interrupt Priority Register n 0x306 8 read-write n 0x0 0x0 PRI6 Priority of interrupt 6 0 8 read-write NVICIP60 Interrupt Priority Register n 0x33C 8 read-write n 0x0 0x0 PRI60 Priority of interrupt 60 0 8 read-write NVICIP61 Interrupt Priority Register n 0x33D 8 read-write n 0x0 0x0 PRI61 Priority of interrupt 61 0 8 read-write NVICIP62 Interrupt Priority Register n 0x33E 8 read-write n 0x0 0x0 PRI62 Priority of interrupt 62 0 8 read-write NVICIP63 Interrupt Priority Register n 0x33F 8 read-write n 0x0 0x0 PRI63 Priority of interrupt 63 0 8 read-write NVICIP64 Interrupt Priority Register n 0x340 8 read-write n 0x0 0x0 PRI64 Priority of interrupt 64 0 8 read-write NVICIP65 Interrupt Priority Register n 0x341 8 read-write n 0x0 0x0 PRI65 Priority of interrupt 65 0 8 read-write NVICIP66 Interrupt Priority Register n 0x342 8 read-write n 0x0 0x0 PRI66 Priority of interrupt 66 0 8 read-write NVICIP67 Interrupt Priority Register n 0x343 8 read-write n 0x0 0x0 PRI67 Priority of interrupt 67 0 8 read-write NVICIP68 Interrupt Priority Register n 0x344 8 read-write n 0x0 0x0 PRI68 Priority of interrupt 68 0 8 read-write NVICIP69 Interrupt Priority Register n 0x345 8 read-write n 0x0 0x0 PRI69 Priority of interrupt 69 0 8 read-write NVICIP7 Interrupt Priority Register n 0x307 8 read-write n 0x0 0x0 PRI7 Priority of interrupt 7 0 8 read-write NVICIP70 Interrupt Priority Register n 0x346 8 read-write n 0x0 0x0 PRI70 Priority of interrupt 70 0 8 read-write NVICIP71 Interrupt Priority Register n 0x347 8 read-write n 0x0 0x0 PRI71 Priority of interrupt 71 0 8 read-write NVICIP72 Interrupt Priority Register n 0x348 8 read-write n 0x0 0x0 PRI72 Priority of interrupt 72 0 8 read-write NVICIP73 Interrupt Priority Register n 0x349 8 read-write n 0x0 0x0 PRI73 Priority of interrupt 73 0 8 read-write NVICIP74 Interrupt Priority Register n 0x34A 8 read-write n 0x0 0x0 PRI74 Priority of interrupt 74 0 8 read-write NVICIP75 Interrupt Priority Register n 0x34B 8 read-write n 0x0 0x0 PRI75 Priority of interrupt 75 0 8 read-write NVICIP76 Interrupt Priority Register n 0x34C 8 read-write n 0x0 0x0 PRI76 Priority of interrupt 76 0 8 read-write NVICIP77 Interrupt Priority Register n 0x34D 8 read-write n 0x0 0x0 PRI77 Priority of interrupt 77 0 8 read-write NVICIP78 Interrupt Priority Register n 0x34E 8 read-write n 0x0 0x0 PRI78 Priority of interrupt 78 0 8 read-write NVICIP79 Interrupt Priority Register n 0x34F 8 read-write n 0x0 0x0 PRI79 Priority of interrupt 79 0 8 read-write NVICIP8 Interrupt Priority Register n 0x308 8 read-write n 0x0 0x0 PRI8 Priority of interrupt 8 0 8 read-write NVICIP80 Interrupt Priority Register n 0x350 8 read-write n 0x0 0x0 PRI80 Priority of interrupt 80 0 8 read-write NVICIP81 Interrupt Priority Register n 0x351 8 read-write n 0x0 0x0 PRI81 Priority of interrupt 81 0 8 read-write NVICIP82 Interrupt Priority Register n 0x352 8 read-write n 0x0 0x0 PRI82 Priority of interrupt 82 0 8 read-write NVICIP83 Interrupt Priority Register n 0x353 8 read-write n 0x0 0x0 PRI83 Priority of interrupt 83 0 8 read-write NVICIP84 Interrupt Priority Register n 0x354 8 read-write n 0x0 0x0 PRI84 Priority of interrupt 84 0 8 read-write NVICIP85 Interrupt Priority Register n 0x355 8 read-write n 0x0 0x0 PRI85 Priority of interrupt 85 0 8 read-write NVICIP86 Interrupt Priority Register n 0x356 8 read-write n 0x0 0x0 PRI86 Priority of interrupt 86 0 8 read-write NVICIP87 Interrupt Priority Register n 0x357 8 read-write n 0x0 0x0 PRI87 Priority of interrupt 87 0 8 read-write NVICIP88 Interrupt Priority Register n 0x358 8 read-write n 0x0 0x0 PRI88 Priority of interrupt 88 0 8 read-write NVICIP89 Interrupt Priority Register n 0x359 8 read-write n 0x0 0x0 PRI89 Priority of interrupt 89 0 8 read-write NVICIP9 Interrupt Priority Register n 0x309 8 read-write n 0x0 0x0 PRI9 Priority of interrupt 9 0 8 read-write NVICIP90 Interrupt Priority Register n 0x35A 8 read-write n 0x0 0x0 PRI90 Priority of interrupt 90 0 8 read-write NVICIP91 Interrupt Priority Register n 0x35B 8 read-write n 0x0 0x0 PRI91 Priority of interrupt 91 0 8 read-write NVICIP92 Interrupt Priority Register n 0x35C 8 read-write n 0x0 0x0 PRI92 Priority of interrupt 92 0 8 read-write NVICIP93 Interrupt Priority Register n 0x35D 8 read-write n 0x0 0x0 PRI93 Priority of interrupt 93 0 8 read-write NVICIP94 Interrupt Priority Register n 0x35E 8 read-write n 0x0 0x0 PRI94 Priority of interrupt 94 0 8 read-write NVICIP95 Interrupt Priority Register n 0x35F 8 read-write n 0x0 0x0 PRI95 Priority of interrupt 95 0 8 read-write NVICIP96 Interrupt Priority Register n 0x360 8 read-write n 0x0 0x0 PRI96 Priority of interrupt 96 0 8 read-write NVICIP97 Interrupt Priority Register n 0x361 8 read-write n 0x0 0x0 PRI97 Priority of interrupt 97 0 8 read-write NVICIP98 Interrupt Priority Register n 0x362 8 read-write n 0x0 0x0 PRI98 Priority of interrupt 98 0 8 read-write NVICIP99 Interrupt Priority Register n 0x363 8 read-write n 0x0 0x0 PRI99 Priority of interrupt 99 0 8 read-write NVICISER0 Interrupt Set Enable Register n 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISER1 Interrupt Set Enable Register n 0x4 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISER2 Interrupt Set Enable Register n 0x8 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISER3 Interrupt Set Enable Register n 0xC 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISPR0 Interrupt Set Pending Register n 0x100 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR1 Interrupt Set Pending Register n 0x104 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR2 Interrupt Set Pending Register n 0x108 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR3 Interrupt Set Pending Register n 0x10C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICSTIR Software Trigger Interrupt Register 0xE00 32 read-write n 0x0 0x0 INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write OPAMP0 General Purpose Operational Amplifier OPAMP 0x0 0x0 0x3 registers n C0 Control Register 0 0x0 8 read-write n 0x0 0x0 EN OPAMP Enable 7 1 read-write 0 OPAMP is disabled and not powered #0 1 OPAMP is enabled and powered #1 LPEN Low-Power Mode Enable 6 1 read-write 0 High-speed mode selected. In this mode, OPAMP has faster slew rate and unity gain bandwidth performance with higher current consumption. #0 1 Low-power mode selected. In this mode, OPAMP has lower current consumption with slower slew rate and unity gain bandwidth performance. #1 MODE OPAMP Mode Select 0 2 read-write 00 Buffer #00 01 Inverting PGA #01 10 General purpose #10 11 Non-inverting PGA #11 C1 Control Register 1 0x1 8 read-write n 0x0 0x0 AMPRF Gains Selector 2 3 read-write AMPRI Gains Selector 0 2 read-write C2 Control Register 2 0x2 8 read-write n 0x0 0x0 AMPNSEL Amplifier Negative Input Terminal Selector. 0 3 read-write 000 Negative input 0 #000 001 Negative input 1 #001 010 Negative input 2 #010 011 Negative input 3 #011 100 Negative input 4 #100 101 Negative input 5 #101 110 Negative input 6 #110 111 Negative input 7 #111 AMPPSEL Amplifier Positive Input Terminal Selector 4 3 read-write 000 Positive input 0 #000 001 Positive input 1 #001 010 Positive input 2 #010 011 Positive input 3 #011 100 Positive input 4 #100 101 Positive input 5 #101 110 Positive input 6 #110 111 Positive input 7 #111 OPAMP1 General Purpose Operational Amplifier OPAMP 0x0 0x0 0x3 registers n C0 Control Register 0 0x0 8 read-write n 0x0 0x0 EN OPAMP Enable 7 1 read-write 0 OPAMP is disabled and not powered #0 1 OPAMP is enabled and powered #1 LPEN Low-Power Mode Enable 6 1 read-write 0 High-speed mode selected. In this mode, OPAMP has faster slew rate and unity gain bandwidth performance with higher current consumption. #0 1 Low-power mode selected. In this mode, OPAMP has lower current consumption with slower slew rate and unity gain bandwidth performance. #1 MODE OPAMP Mode Select 0 2 read-write 00 Buffer #00 01 Inverting PGA #01 10 General purpose #10 11 Non-inverting PGA #11 C1 Control Register 1 0x1 8 read-write n 0x0 0x0 AMPRF Gains Selector 2 3 read-write AMPRI Gains Selector 0 2 read-write C2 Control Register 2 0x2 8 read-write n 0x0 0x0 AMPNSEL Amplifier Negative Input Terminal Selector. 0 3 read-write 000 Negative input 0 #000 001 Negative input 1 #001 010 Negative input 2 #010 011 Negative input 3 #011 100 Negative input 4 #100 101 Negative input 5 #101 110 Negative input 6 #110 111 Negative input 7 #111 AMPPSEL Amplifier Positive Input Terminal Selector 4 3 read-write 000 Positive input 0 #000 001 Positive input 1 #001 010 Positive input 2 #010 011 Positive input 3 #011 100 Positive input 4 #100 101 Positive input 5 #101 110 Positive input 6 #110 111 Positive input 7 #111 OSC Oscillator OSC 0x0 0x0 0x1 registers n CR OSC Control Register 0x0 8 read-write n 0x0 0x0 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 PDB0 Programmable Delay Block PDB0 0x0 0x0 0x198 registers n PDB0 72 CH0C1 Channel n Control Register 1 0x20 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH0DLY0 Channel n Delay 0 Register 0x30 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH0DLY1 Channel n Delay 1 Register 0x38 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH0S Channel n Status Register 0x28 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 CH1C1 Channel n Control Register 1 0x58 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH1DLY0 Channel n Delay 0 Register 0x70 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH1DLY1 Channel n Delay 1 Register 0x7C 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH1S Channel n Status Register 0x64 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 CNT Counter Register 0x8 32 read-only n 0x0 0x0 CNT PDB Counter 0 16 read-only DACINT0 DAC Interval n Register 0x2A8 32 read-write n 0x0 0x0 INT DAC Interval 0 16 read-write DACINT1 DAC Interval n Register 0x404 32 read-write n 0x0 0x0 INT DAC Interval 0 16 read-write DACINTC0 DAC Interval Trigger n Control Register 0x2A0 32 read-write n 0x0 0x0 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 DACINTC1 DAC Interval Trigger n Control Register 0x3F8 32 read-write n 0x0 0x0 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 IDLY Interrupt Delay Register 0xC 32 read-write n 0x0 0x0 IDLY PDB Interrupt Delay 0 16 read-write MOD Modulus Register 0x4 32 read-write n 0x0 0x0 MOD PDB Modulus. 0 16 read-write PODLY Pulse-Out n Delay Register 0x194 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write POEN Pulse-Out n Enable Register 0x190 32 read-write n 0x0 0x0 POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 SC Status and Control Register 0x0 32 read-write n 0x0 0x0 CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 DMAEN DMA Enable 15 1 read-write 0 DMA disabled #0 1 DMA enabled #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 LDOK Load OK 0 1 read-write MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1 #00 01 Multiplication factor is 10 #01 10 Multiplication factor is 20 #10 11 Multiplication factor is 40 #11 PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled #1 PDBIE PDB Interrupt Enable. 5 1 read-write 0 PDB interrupt disabled #0 1 PDB interrupt enabled #1 PDBIF PDB Interrupt Flag 6 1 read-write PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 SWTRIG Software Trigger 16 1 write-only TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected #0000 0001 Trigger-In 1 is selected #0001 0010 Trigger-In 2 is selected #0010 0011 Trigger-In 3 is selected #0011 0100 Trigger-In 4 is selected #0100 0101 Trigger-In 5 is selected #0101 0110 Trigger-In 6 is selected #0110 0111 Trigger-In 7 is selected #0111 1000 Trigger-In 8 is selected #1000 1001 Trigger-In 9 is selected #1001 1010 Trigger-In 10 is selected #1010 1011 Trigger-In 11 is selected #1011 1100 Trigger-In 12 is selected #1100 1101 Trigger-In 13 is selected #1101 1110 Trigger-In 14 is selected #1110 1111 Software trigger is selected #1111 PIT Periodic Interrupt Timer PIT 0x0 0x0 0x140 registers n PIT0 68 PIT1 69 PIT2 70 PIT3 71 CVAL0 Current Timer Value Register 0x208 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL1 Current Timer Value Register 0x31C 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL2 Current Timer Value Register 0x440 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL3 Current Timer Value Register 0x574 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only LDVAL0 Timer Load Value Register 0x200 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write LDVAL1 Timer Load Value Register 0x310 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write LDVAL2 Timer Load Value Register 0x430 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write LDVAL3 Timer Load Value Register 0x560 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write MCR PIT Module Control Register 0x0 32 read-write n 0x0 0x0 FRZ Freeze 0 1 read-write 0 Timers continue to run in debug mode. #0 1 Timers are stopped in debug mode. #1 MDIS Module Disable 1 1 read-write 0 Clock for PIT Timers is enabled. #0 1 Clock for PIT Timers is disabled. #1 TCTRL0 Timer Control Register 0x210 32 read-write n 0x0 0x0 TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL1 Timer Control Register 0x328 32 read-write n 0x0 0x0 TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL2 Timer Control Register 0x450 32 read-write n 0x0 0x0 TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL3 Timer Control Register 0x588 32 read-write n 0x0 0x0 TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TFLG0 Timer Flag Register 0x218 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 TFLG1 Timer Flag Register 0x334 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 TFLG2 Timer Flag Register 0x460 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 TFLG3 Timer Flag Register 0x59C 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 PMC Mode Controller PMC 0x0 0x0 0x3 registers n LVD_LVW 20 LVDSC1 Low Voltage Detect Status and Control 1 Register 0x0 8 read-write n 0x0 0x0 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1. #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (VLVD = VLVDL) #00 01 High trip point selected (VLVD = VLVDH) #01 LVDSC2 Low Voltage Detect Status and Control 2 Register 0x1 8 read-write n 0x0 0x0 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1. #1 LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1H/L) #00 01 Mid 1 trip point selected (VLVW = VLVW2H/L) #01 10 Mid 2 trip point selected (VLVW = VLVW3H/L) #10 11 High trip point selected (VLVW = VLVW4H/L) #11 REGSC Regulator Status and Control Register 0x2 8 read-write n 0x0 0x0 BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator in Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 TRAMPO For devices with FlexNVM: Traditional RAM Power Option For devices with program flash only: Reserved 4 1 read-write 0 For devices with FlexNVM: Traditional RAM not powered in VLLS2 For devices with program flash only: No effect #0 1 For devices with FlexNVM: Traditional RAM powered in VLLS2 For devices with program flash only: No effect #1 VLPRS Very Low Power Run Status 3 1 read-only 0 MCU is not in VLPR mode #0 1 MCU is in VLPR mode #1 PORTA Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTA 87 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTB Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTB 88 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTC Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTC 89 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTD Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTD 90 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTE Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTE 91 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PTA General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTA 87 GPIOA_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic zero. #1 GPIOA_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general purpose input, if configured for the GPIO function #0 1 Pin is configured for general purpose output, if configured for the GPIO function #1 GPIOA_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic zero or is configured for use by digital function. #0 1 Pin logic level is logic one. #1 GPIOA_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin provided pin is configured for General Purpose Output. #0 1 Logic level 1 is driven on pin provided pin is configured for General Purpose Output. #1 GPIOA_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic one. #1 GPIOA_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTB General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTB 88 GPIOB_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic zero. #1 GPIOB_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general purpose input, if configured for the GPIO function #0 1 Pin is configured for general purpose output, if configured for the GPIO function #1 GPIOB_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic zero or is configured for use by digital function. #0 1 Pin logic level is logic one. #1 GPIOB_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin provided pin is configured for General Purpose Output. #0 1 Logic level 1 is driven on pin provided pin is configured for General Purpose Output. #1 GPIOB_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic one. #1 GPIOB_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTC General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTC 89 GPIOC_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic zero. #1 GPIOC_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general purpose input, if configured for the GPIO function #0 1 Pin is configured for general purpose output, if configured for the GPIO function #1 GPIOC_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic zero or is configured for use by digital function. #0 1 Pin logic level is logic one. #1 GPIOC_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin provided pin is configured for General Purpose Output. #0 1 Logic level 1 is driven on pin provided pin is configured for General Purpose Output. #1 GPIOC_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic one. #1 GPIOC_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTD General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTD 90 GPIOD_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic zero. #1 GPIOD_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general purpose input, if configured for the GPIO function #0 1 Pin is configured for general purpose output, if configured for the GPIO function #1 GPIOD_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic zero or is configured for use by digital function. #0 1 Pin logic level is logic one. #1 GPIOD_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin provided pin is configured for General Purpose Output. #0 1 Logic level 1 is driven on pin provided pin is configured for General Purpose Output. #1 GPIOD_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic one. #1 GPIOD_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTE General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTE 91 GPIOE_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic zero. #1 GPIOE_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general purpose input, if configured for the GPIO function #0 1 Pin is configured for general purpose output, if configured for the GPIO function #1 GPIOE_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic zero or is configured for use by digital function. #0 1 Pin logic level is logic one. #1 GPIOE_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin provided pin is configured for General Purpose Output. #0 1 Logic level 1 is driven on pin provided pin is configured for General Purpose Output. #1 GPIOE_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic one. #1 GPIOE_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 RFSYS System register file RFSYS 0x0 0x0 0x20 registers n REG0 Register file register 0x0 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG1 Register file register 0x4 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG2 Register file register 0xC 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG3 Register file register 0x18 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG4 Register file register 0x28 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG5 Register file register 0x3C 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG6 Register file register 0x54 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG7 Register file register 0x70 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write RFVBAT VBAT register file RFVBAT 0x0 0x0 0x20 registers n REG0 VBAT register file register 0x0 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG1 VBAT register file register 0x4 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG2 VBAT register file register 0xC 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG3 VBAT register file register 0x18 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG4 VBAT register file register 0x28 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG5 VBAT register file register 0x3C 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG6 VBAT register file register 0x54 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG7 VBAT register file register 0x70 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write RNG Random Number Generator RNG 0x0 0x0 0x18 registers n RNG 23 CMD RNGB Command Register 0x4 32 read-write n 0x0 0x0 CE Clear error. 5 1 write-only 0 Do not clear errors and interrupt. #0 1 Clear errors and interrupt. #1 CI Clear interrupt. 4 1 write-only 0 Do not clear interrupt. #0 1 Clear interrupt. #1 GS Generate seed. 1 1 read-write 0 Not in seed generation mode. #0 1 Generate seed mode. #1 SR Software reset. 6 1 write-only 0 Do not perform a software reset. #0 1 Software reset. #1 ST Self test. 0 1 read-write 0 Not in self test mode. #0 1 Self test mode. #1 CR RNGB Control Register 0x8 32 read-write n 0x0 0x0 AR Auto-reseed. 4 1 read-write 0 Do not enable automatic reseeding. #0 1 Enable automatic reseeding. #1 FUFMOD FIFO underflow response mode. 0 2 read-write 00 Return all zeros and set RNG_ESR[FUFE] #00 01 Return all zeros and set RNG_ESR[FUFE] #01 10 Generate bus transfer error #10 11 Generate interrupt and return all zeros (Overrides RNG_CR[MASKERR]) #11 MASKDONE Mask done interrupt. 5 1 read-write 0 No mask applied. #0 1 Mask applied. #1 MASKERR Mask error interrupt. 6 1 read-write 0 No mask applied. #0 1 Mask applied to the error interrupt. #1 ESR RNGB Error Status Register 0x10 32 read-only n 0x0 0x0 FUFE FIFO underflow error 4 1 read-only 0 FIFO underflow has not occurred. #0 1 FIFO underflow has occurred #1 LFE Linear feedback shift register (LFSR) error. 0 1 read-only 0 LFSRs are working properly. #0 1 LFSR failure has occurred. #1 OSCE Oscillator error. 1 1 read-only 0 RNG oscillator is working properly. #0 1 Problem detected with the RNG oscillator. #1 SATE Statistical test error. 3 1 read-only 0 RNGB has not failed the statistical tests. #0 1 RNGB has failed the statistical tests during initialization. #1 STE Self test error. 2 1 read-only 0 RNGB has not failed self test. #0 1 RNGB has failed self test. #1 OUT RNGB Output FIFO 0x14 32 read-only n 0x0 0x0 RANDOUT Random Output 0 32 read-only SR RNGB Status Register 0xC 32 read-only n 0x0 0x0 BUSY Busy. 1 1 read-only 0 Not busy. #0 1 Busy. #1 ERR Error. 16 1 read-only 0 No error. #0 1 Error detected. #1 FIFO_LVL FIFO level. 8 4 read-only FIFO_SIZE FIFO size. 12 4 read-only NSDN New seed done. 6 1 read-only RS Reseed needed. 3 1 read-only 0 RNGB does not need to be reseeded. #0 1 RNGB needs to be reseeded. #1 SDN Seed done. 5 1 read-only 0 Seed generation process not complete. #0 1 Completed seed generation since the last reset. #1 SLP Sleep. 2 1 read-only 0 RNGB is not in sleep mode. #0 1 RNGB is in sleep mode. #1 STATPF Statistics test pass fail. 24 8 read-only 0 Pass. #0 1 Fail. #1 STDN Self test done. 4 1 read-only 0 Self test not complete. #0 1 Completed a self test since the last reset. #1 ST_PF Self Test Pass Fail. 21 3 read-only 0 Pass. #0 1 Fail. #1 VER RNGB Version ID Register 0x0 32 read-only n 0x0 0x0 MAJOR Major version number. 8 8 read-only MINOR Minor version number. 0 8 read-only TYPE Random number generator type 28 4 read-only 0000 RNGA #0000 0001 RNGB (This is the type used in this module) #0001 0010 RNGC #0010 RTC Secure Real Time Clock RTC 0x0 0x0 0x808 registers n RTC 66 CR RTC Control Register 0x10 32 read-write n 0x0 0x0 CLKO Clock Output 9 1 read-write 0 The 32kHz clock is output to other peripherals #0 1 The 32kHz clock is not output to other peripherals #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 SC16P Oscillator 16pF load configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF load configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF load configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF load configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 SWR Software Reset 0 1 read-write 0 No effect #0 1 Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers. The SWR bit is cleared after VBAT POR and by software explicitly clearing it. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts and the chip is powered down. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 LR RTC Lock Register 0x18 32 read-write n 0x0 0x0 CRL Control Register Lock 4 1 read-write 0 Control register is locked and writes are ignored. #0 1 Control register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock register is locked and writes are ignored. #0 1 Lock register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status register is locked and writes are ignored. #0 1 Status register is not locked and writes complete as normal. #1 TCL Time Compensation Lock 3 1 read-write 0 Time compensation register is locked and writes are ignored. #0 1 Time compensation register is not locked and writes complete as normal. #1 RAR RTC Read Access Register 0x804 32 read-write n 0x0 0x0 CRR Control Register Read 4 1 read-write 0 Reads to the control register are ignored. #0 1 Reads to the control register complete as normal. #1 IERR Interrupt Enable Register Read 7 1 read-write 0 Reads to the interrupt enable register are ignored. #0 1 Reads to the interrupt enable register complete as normal. #1 LRR Lock Register Read 6 1 read-write 0 Reads to the lock register are ignored. #0 1 Reads to the lock register complete as normal. #1 SRR Status Register Read 5 1 read-write 0 Reads to the status register are ignored. #0 1 Reads to the status register complete as normal. #1 TARR Time Alarm Register Read 2 1 read-write 0 Reads to the time alarm register are ignored. #0 1 Reads to the time alarm register complete as normal. #1 TCRR Time Compensation Register Read 3 1 read-write 0 Reads to the time compensation register are ignored. #0 1 Reads to the time compensation register complete as normal. #1 TPRR Time Prescaler Register Read 1 1 read-write 0 Reads to the time prescaler register are ignored. #0 1 Reads to the time prescaler register complete as normal. #1 TSRR Time Seconds Register Read 0 1 read-write 0 Reads to the time seconds register are ignored. #0 1 Reads to the time seconds register complete as normal. #1 SR RTC Status Register 0x14 32 read-write n 0x0 0x0 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAR RTC Time Alarm Register 0x8 32 read-write n 0x0 0x0 TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write n 0x0 0x0 CIC Compensation Interval Counter 24 8 read-only CIR Compensation Interval Register 8 8 read-write TCR Time Compensation Register 0 8 read-write 0 Time prescaler register overflows every 32768 clock cycles. #0 1 Time prescaler register overflows every 32767 clock cycles. #1 10000000 Time prescaler register overflows every 32896 clock cycles. #10000000 1111111 Time prescaler register overflows every 32641 clock cycles. #1111111 11111111 Time prescaler register overflows every 32769 clock cycles. #11111111 TCV Time Compensation Value 16 8 read-only TPR RTC Time Prescaler Register 0x4 32 read-write n 0x0 0x0 TPR Time Prescaler Register 0 16 read-write TSR RTC Time Seconds Register 0x0 32 read-write n 0x0 0x0 TSR Time Seconds Register 0 32 read-write WAR RTC Write Access Register 0x800 32 read-write n 0x0 0x0 CRW Control Register Write 4 1 read-write 0 Writes to the control register are ignored. #0 1 Writes to the control register complete as normal. #1 IERW Interrupt Enable Register Write 7 1 read-write 0 Writes to the interupt enable register are ignored. #0 1 Writes to the interrupt enable register complete as normal. #1 LRW Lock Register Write 6 1 read-write 0 Writes to the lock register are ignored. #0 1 Writes to the lock register complete as normal. #1 SRW Status Register Write 5 1 read-write 0 Writes to the status register are ignored. #0 1 Writes to the status register complete as normal. #1 TARW Time Alarm Register Write 2 1 read-write 0 Writes to the time alarm register are ignored. #0 1 Writes to the time alarm register complete as normal. #1 TCRW Time Compensation Register Write 3 1 read-write 0 Writes to the time compensation register are ignored. #0 1 Writes to the time compensation register complete as normal. #1 TPRW Time Prescaler Register Write 1 1 read-write 0 Writes to the time prescaler register are ignored. #0 1 Writes to the time prescaler register complete as normal. #1 TSRW Time Seconds Register Write 0 1 read-write 0 Writes to the time seconds register are ignored. #0 1 Writes to the time seconds register complete as normal. #1 SDHC Secured Digital Host Controller SDHC 0x0 0x0 0x100 registers n SDHC 80 AC12ERR Auto CMD12 Error Status Register 0x3C 32 read-only n 0x0 0x0 AC12CE Auto CMD12 CRC Error 3 1 read-only 0 No CRC error #0 1 CRC Error met in auto CMD12 Response #1 AC12EBE Auto CMD12 End Bit Error 2 1 read-only 0 No error #0 1 End bit error generated #1 AC12IE Auto CMD12 Index Error 4 1 read-only 0 No error #0 1 Error, the CMD index in response is not CMD12 #1 AC12NE Auto CMD12 Not Executed 0 1 read-only 0 Executed #0 1 Not executed #1 AC12TOE Auto CMD12 Timeout Error 1 1 read-only 0 No error #0 1 Time out #1 CNIBAC12E Command Not Issued By Auto CMD12 Error 7 1 read-only 0 No error #0 1 Not issued #1 ADMAES ADMA Error Status Register 0x54 32 read-only n 0x0 0x0 ADMADCE ADMA Descritor Error 3 1 read-only 0 No error #0 1 Error #1 ADMAES ADMA Error State (when ADMA Error is occurred.) 0 2 read-only ADMALME ADMA Length Mismatch Error 2 1 read-only 0 No error #0 1 Error #1 ADSADDR ADMA System Address Register 0x58 32 read-write n 0x0 0x0 ADSADDR ADMA System Address 2 30 read-write BLKATTR Block Attributes Register 0x4 32 read-write n 0x0 0x0 BLKCNT Blocks Count For Current Transfer 16 16 read-write 0 Stop count #0 1 1 block #1 10 2 blocks #10 1111111111111111 65535 blocks #1111111111111111 BLKSIZE Transfer Block Size 0 13 read-write 0 No data transfer #0 1 1 Byte #1 10 2 Bytes #10 100 4 Bytes #100 1000000000 512 Bytes #1000000000 100000000000 2048 Bytes #100000000000 1000000000000 4096 Bytes #1000000000000 11 3 Bytes #11 111111111 511 Bytes #111111111 CMDARG Command Argument Register 0x8 32 read-write n 0x0 0x0 CMDARG Command Argument 0 32 read-write CMDRSP0 Command Response 0 0x10 32 read-only n 0x0 0x0 CMDRSP0 Command Response 0 0 32 read-only CMDRSP1 Command Response 1 0x14 32 read-only n 0x0 0x0 CMDRSP1 Command Response 1 0 32 read-only CMDRSP2 Command Response 2 0x18 32 read-only n 0x0 0x0 CMDRSP2 Command Response 2 0 32 read-only CMDRSP3 Command Response 3 0x1C 32 read-only n 0x0 0x0 CMDRSP3 Command Response 3 0 32 read-only DATPORT Buffer Data Port Register 0x20 32 read-write n 0x0 0x0 DATCONT Data Content 0 32 read-write DSADDR DMA System Address Register 0x0 32 read-write n 0x0 0x0 DSADDR DMA System Address 2 30 read-write FEVT Force Event Register 0x50 32 write-only n 0x0 0x0 AC12CE Force Event Auto Command 12 CRC Error 2 1 write-only AC12E Force Event Auto Command 12 Error 24 1 write-only AC12EBE Force Event Auto Command 12 End Bit Error 3 1 write-only AC12IE Force Event Auto Command 12 Index Error 4 1 write-only AC12NE Force Event Auto Command 12 Not Executed 0 1 write-only AC12TOE Force Event Auto Command 12 Time Out Error 1 1 write-only CCE Force Event Command CRC Error 17 1 write-only CEBE Force Event Command End Bit Error 18 1 write-only CIE Force Event Command Index Error 19 1 write-only CINT Force Event Card Interrupt 31 1 write-only CNIBAC12E Force Event Command Not Executed By Auto Command 12 Error 7 1 write-only CTOE Force Event Command Time Out Error 16 1 write-only DCE Force Event Data CRC Error 21 1 write-only DEBE Force Event Data End Bit Error 22 1 write-only DMAE Force Event DMA Error 28 1 write-only DTOE Force Event Data Time Out Error 20 1 write-only HOSTVER Host Controller Version 0xFC 32 read-only n 0x0 0x0 SVN Specification Version Number 0 8 read-only 1 SD host specification version 2.0, supports test event register and ADMA. #1 VVN Vendor Version Number 8 8 read-only 0 Freescale SDHC version 1.0 #0 10000 Freescale SDHC version 2.0 #10000 10001 Freescale SDHC version 2.1 #10001 10010 Freescale SDHC version 2.2 #10010 HTCAPBLT Host Controller Capabilities 0x40 32 read-only n 0x0 0x0 ADMAS ADMA Support 20 1 read-only 0 Advanced DMA not supported #0 1 Advanced DMA supported #1 DMAS DMA Support 22 1 read-only 0 DMA not supported #0 1 DMA supported #1 HSS High Speed Support 21 1 read-only 0 High speed not supported #0 1 High speed supported #1 MBL Max Block Length 16 3 read-only 000 512 bytes #000 001 1024 bytes #001 010 2048 bytes #010 011 4096 bytes #011 SRS Suspend/Resume Support 23 1 read-only 0 Not supported #0 1 Supported #1 VS18 Voltage Support 1.8 V 26 1 read-only 0 1.8 V not supported #0 1 1.8 V supported #1 VS30 Voltage Support 3.0 V 25 1 read-only 0 3.0 V not supported #0 1 3.0 V supported #1 VS33 Voltage Support 3.3 V 24 1 read-only 0 3.3 V not supported #0 1 3.3 V supported #1 IRQSIGEN Interrupt Signal Enable Register 0x38 32 read-write n 0x0 0x0 AC12EIEN Auto CMD12 Error Interrupt Enable 24 1 read-write 0 Masked #0 1 Enabled #1 BGEIEN Block Gap Event Interrupt Enable 2 1 read-write 0 Masked #0 1 Enabled #1 BRRIEN Buffer Read Ready Interrupt Enable 5 1 read-write 0 Masked #0 1 Enabled #1 BWRIEN Buffer Write Ready Interrupt Enable 4 1 read-write 0 Masked #0 1 Enabled #1 CCEIEN Command CRC Error Interrupt Enable 17 1 read-write 0 Masked #0 1 Enabled #1 CCIEN Command Complete Interrupt Enable 0 1 read-write 0 Masked #0 1 Enabled #1 CEBEIEN Command End Bit Error Interrupt Enable 18 1 read-write 0 Masked #0 1 Enabled #1 CIEIEN Command Index Error Interrupt Enable 19 1 read-write 0 Masked #0 1 Enabled #1 CINSIEN Card Insertion Interrupt Enable 6 1 read-write 0 Masked #0 1 Enabled #1 CINTIEN Card Interrupt Enable 8 1 read-write 0 Masked #0 1 Enabled #1 CRMIEN Card Removal Interrupt Enable 7 1 read-write 0 Masked #0 1 Enabled #1 CTOEIEN Command Timeout Error Interrupt Enable 16 1 read-write 0 Masked #0 1 Enabled #1 DCEIEN Data CRC Error Interrupt Enable 21 1 read-write 0 Masked #0 1 Enabled #1 DEBEIEN Data End Bit Error Interrupt Enable 22 1 read-write 0 Masked #0 1 Enabled #1 DINTIEN DMA Interrupt Enable 3 1 read-write 0 Masked #0 1 Enabled #1 DMAEIEN DMA Error Interrupt Enable 28 1 read-write 0 Masked #0 1 Enabled #1 DTOEIEN Data Timeout Error Interrupt Enable 20 1 read-write 0 Masked #0 1 Enabled #1 TCIEN Transfer Complete Interrupt Enable 1 1 read-write 0 Masked #0 1 Enabled #1 IRQSTAT Interrupt Status Register 0x30 32 read-write n 0x0 0x0 AC12E Auto CMD12 Error 24 1 read-write 0 No Error #0 1 Error #1 BGE Block Gap Event 2 1 read-write 0 No block gap event #0 1 Transaction stopped at block gap #1 BRR Buffer Read Ready 5 1 read-write 0 Not ready to read buffer #0 1 Ready to read buffer #1 BWR Buffer Write Ready 4 1 read-write 0 Not ready to write buffer #0 1 Ready to write buffer #1 CC Command Complete 0 1 read-write 0 Command not complete #0 1 Command complete #1 CCE Command CRC Error 17 1 read-write 0 No Error #0 1 CRC Error Generated #1 CEBE Command End Bit Error 18 1 read-write 0 No Error #0 1 End Bit Error Generated #1 CIE Command Index Error 19 1 read-write 0 No Error #0 1 Error #1 CINS Card Insertion 6 1 read-write 0 Card state unstable or removed #0 1 Card inserted #1 CINT Card Interrupt 8 1 read-write 0 No Card Interrupt #0 1 Generate Card Interrupt #1 CRM Card Removal 7 1 read-write 0 Card state unstable or inserted #0 1 Card removed #1 CTOE Command Timeout Error 16 1 read-write 0 No Error #0 1 Time out #1 DCE Data CRC Error 21 1 read-write 0 No Error #0 1 Error #1 DEBE Data End Bit Error 22 1 read-write 0 No Error #0 1 Error #1 DINT DMA Interrupt 3 1 read-write 0 No DMA Interrupt #0 1 DMA Interrupt is generated #1 DMAE DMA Error 28 1 read-write 0 No Error #0 1 Error #1 DTOE Data Timeout Error 20 1 read-write 0 No Error #0 1 Time out #1 TC Transfer Complete 1 1 read-write 0 Transfer not complete #0 1 Transfer complete #1 IRQSTATEN Interrupt Status Enable Register 0x34 32 read-write n 0x0 0x0 AC12ESEN Auto CMD12 Error Status Enable 24 1 read-write 0 Masked #0 1 Enabled #1 BGESEN Block Gap Event Status Enable 2 1 read-write 0 Masked #0 1 Enabled #1 BRRSEN Buffer Read Ready Status Enable 5 1 read-write 0 Masked #0 1 Enabled #1 BWRSEN Buffer Write Ready Status Enable 4 1 read-write 0 Masked #0 1 Enabled #1 CCESEN Command CRC Error Status Enable 17 1 read-write 0 Masked #0 1 Enabled #1 CCSEN Command Complete Status Enable 0 1 read-write 0 Masked #0 1 Enabled #1 CEBESEN Command End Bit Error Status Enable 18 1 read-write 0 Masked #0 1 Enabled #1 CIESEN Command Index Error Status Enable 19 1 read-write 0 Masked #0 1 Enabled #1 CINSEN Card Insertion Status Enable 6 1 read-write 0 Masked #0 1 Enabled #1 CINTSEN Card Interrupt Status Enable 8 1 read-write 0 Masked #0 1 Enabled #1 CRMSEN Card Removal Status Enable 7 1 read-write 0 Masked #0 1 Enabled #1 CTOESEN Command Timeout Error Status Enable 16 1 read-write 0 Masked #0 1 Enabled #1 DCESEN Data CRC Error Status Enable 21 1 read-write 0 Masked #0 1 Enabled #1 DEBESEN Data End Bit Error Status Enable 22 1 read-write 0 Masked #0 1 Enabled #1 DINTSEN DMA Interrupt Status Enable 3 1 read-write 0 Masked #0 1 Enabled #1 DMAESEN DMA Error Status Enable 28 1 read-write 0 Masked #0 1 Enabled #1 DTOESEN Data Timeout Error Status Enable 20 1 read-write 0 Masked #0 1 Enabled #1 TCSEN Transfer Complete Status Enable 1 1 read-write 0 Masked #0 1 Enabled #1 MMCBOOT MMC Boot Register 0xC4 32 read-write n 0x0 0x0 AUTOSABGEN no description available 7 1 read-write BOOTACK Boot ack mode select 4 1 read-write 0 No ack #0 1 Ack #1 BOOTBLKCNT no description available 16 16 read-write BOOTEN Boot mode enable 6 1 read-write 0 Fast boot disable #0 1 Fast boot enable #1 BOOTMODE Boot mode select 5 1 read-write 0 Normal boot #0 1 Alternative boot #1 DTOCVACK Boot ACK time out counter value. 0 4 read-write 0000 SDCLK x 2^8 #0000 0001 SDCLK x 2^9 #0001 0010 SDCLK x 2^10 #0010 0011 SDCLK x 2^11 #0011 0100 SDCLK x 2^12 #0100 0101 SDCLK x 2^13 #0101 0110 SDCLK x 2^14 #0110 0111 SDCLK x 2^15 #0111 1110 SDCLK x 2^22 #1110 PROCTL Protocol Control Register 0x28 32 read-write n 0x0 0x0 CDSS Card Detect Signal Selection 7 1 read-write 0 Card detection level is selected (for normal purpose) #0 1 Card detection test level is selected (for test purpose) #1 CDTL Card Detect Test Level 6 1 read-write 0 Card detect test level is 0, no card inserted #0 1 Card detect test level is 1, card inserted #1 CREQ Continue Request 17 1 read-write 0 No effect #0 1 Restart #1 D3CD DAT3 as Card Detection Pin 3 1 read-write 0 DAT3 does not monitor card Insertion #0 1 DAT3 as card detection pin #1 DMAS DMA Select 8 2 read-write 00 No DMA or simple DMA is selected #00 01 ADMA1 is selected #01 10 ADMA2 is selected #10 DTW Data Transfer Width 1 2 read-write 00 1-bit mode #00 01 4-bit mode #01 10 8-bit mode #10 EMODE Endian Mode 4 2 read-write 00 Big endian mode #00 01 Half word big endian mode #01 10 Little endian mode #10 IABG Interrupt At Block Gap 19 1 read-write 0 Disabled #0 1 Enabled #1 LCTL LED Control 0 1 read-write 0 LED off #0 1 LED on #1 RWCTL Read Wait Control 18 1 read-write 0 Disable read wait control, and stop SD clock at block gap when SABGREQ bit is set. #0 1 Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set. #1 SABGREQ Stop At Block Gap Request 16 1 read-write 0 Transfer #0 1 Stop #1 WECINS Wakeup Event Enable On SD Card Insertion 25 1 read-write 0 Disabled #0 1 Enabled #1 WECINT Wakeup Event Enable On Card Interrupt 24 1 read-write 0 Disabled #0 1 Enabled #1 WECRM Wakeup Event Enable On SD Card Removal 26 1 read-write 0 Disabled #0 1 Enabled #1 PRSSTAT Present State Register 0x24 32 read-only n 0x0 0x0 BREN Buffer Read Enable 11 1 read-only 0 Read disable, valid data less than the watermark level exist in the buffer. #0 1 Read enable, valid data greater than the watermark level exist in the buffer. #1 BWEN Buffer Write Enable 10 1 read-only 0 Write disable, the buffer can hold valid data less than the write watermark level. #0 1 Write enable, the buffer can hold valid data greater than the write watermark level. #1 CDIHB Command Inhibit (DAT) 1 1 read-only 0 Can issue command which uses the DAT line #0 1 Cannot issue command which uses the DAT line #1 CIHB Command Inhibit (CMD) 0 1 read-only 0 Can issue command using only CMD line #0 1 Cannot issue command #1 CINS Card Inserted 16 1 read-only 0 Power on reset or no card #0 1 Card inserted #1 CLSL CMD Line Signal Level 23 1 read-only DLA Data Line Active 2 1 read-only 0 DAT line inactive #0 1 DAT line active #1 DLSL DAT Line Signal Level 24 8 read-only HCKOFF System Clock Gated Off Internally 5 1 read-only 0 System clock is active #0 1 System clock is gated off #1 IPGOFF Bus Clock Gated Off Internally 4 1 read-only 0 Bus clock is active #0 1 Bus clock is gated off #1 PEROFF SDHC clock Gated Off Internally 6 1 read-only 0 SDHC clock is active #0 1 SDHC clock is gated off #1 RTA Read Transfer Active 9 1 read-only 0 No valid data #0 1 Transferring data #1 SDOFF SD Clock Gated Off Internally 7 1 read-only 0 SD clock is active #0 1 SD clock is gated off #1 SDSTB SD Clock Stable 3 1 read-only 0 Clock is changing frequency and not stable #0 1 Clock is stable #1 WTA Write Transfer Active 8 1 read-only 0 No valid data #0 1 Transferring data #1 SYSCTL System Control Register 0x2C 32 read-write n 0x0 0x0 DTOCV Data Timeout Counter Value 16 4 read-write 0000 SDCLK x 213 #0000 0001 SDCLK x 214 #0001 1110 SDCLK x 227 #1110 DVS Divisor 4 4 read-write 0 Divisor by 1 #0 1 Divisor by 2 #1 1110 Divisor by 15 #1110 1111 Divisor by 16 #1111 HCKEN System Clock Enable 1 1 read-write 0 System clock will be internally gated off #0 1 System clock will not be automatically gated off #1 INITA Initialization Active 27 1 read-write IPGEN IPG Clock Enable 0 1 read-write 0 Bus clock will be internally gated off #0 1 Bus clock will not be automatically gated off #1 PEREN Peripheral Clock Enable 2 1 read-write 0 SDHC clock will be internally gated off #0 1 SDHC clock will not be automatically gated off #1 RSTA Software Reset For ALL 24 1 write-only 0 No reset #0 1 Reset #1 RSTC Software Reset For CMD Line 25 1 write-only 0 No reset #0 1 Reset #1 RSTD Software Reset For DAT Line 26 1 write-only 0 No reset #0 1 Reset #1 SDCLKEN SD Clock Enable 3 1 read-write SDCLKFS SDCLK Frequency Select 8 8 read-write 1 Base clock divided by 2 #1 10 Base clock divided by 4 #10 100 Base clock divided by 8 #100 1000 Base clock divided by 16 #1000 10000 Base clock divided by 32 #10000 100000 Base clock divided by 64 #100000 1000000 Base clock divided by 128 #1000000 10000000 Base clock divided by 256 #10000000 VENDOR Vendor Specific Register 0xC0 32 read-write n 0x0 0x0 EXBLKNU Exact block number block read enable for SDIO CMD53 1 1 read-write 0 none exact block read. #0 1 Exact block read for SDIO CMD53. #1 EXTDMAEN External DMA Request Enable 0 1 read-write 0 In any scenario, SDHC does not send out external DMA request. #0 1 When internal DMA is not active, the external DMA request will be sent out. #1 INTSTVAL Internal State Value 16 8 read-only WML Watermark Level Register 0x44 32 read-write n 0x0 0x0 RDWML Read Watermark Level 0 8 read-write WRBRSTLEN no description available 24 5 read-only WRWML Write Watermark Level 16 8 read-write XFERTYP Transfer Type Register 0xC 32 read-write n 0x0 0x0 AC12EN Auto CMD12 Enable 2 1 read-write 0 Disable #0 1 Enable #1 BCEN Block Count Enable 1 1 read-write 0 Disable #0 1 Enable #1 CCCEN Command CRC Check Enable 19 1 read-write 0 Disable #0 1 Enable #1 CICEN Command Index Check Enable 20 1 read-write 0 Disable #0 1 Enable #1 CMDINX Command Index 24 6 read-write CMDTYP Command Type 22 2 read-write 00 Normal other commands #00 01 Suspend CMD52 for writing bus suspend in CCCR #01 10 Resume CMD52 for writing function select in CCCR #10 11 Abort CMD12, CMD52 for writing I/O abort in CCCR #11 DMAEN DMA Enable 0 1 read-write 0 Disable #0 1 Enable #1 DPSEL Data Present Select 21 1 read-write 0 No data present #0 1 Data present #1 DTDSEL Data Transfer Direction Select 4 1 read-write 0 Write (host to card) #0 1 Read (card to host) #1 MSBSEL Multi/Single Block Select 5 1 read-write 0 Single block #0 1 Multiple blocks #1 RSPTYP Response Type Select 16 2 read-write 00 No response #00 01 Response length 136 #01 10 Response length 48 #10 11 Response length 48, check busy after response #11 SIM System Integration Module SIM 0x0 0x0 0x1064 registers n CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write n 0x0 0x0 OUTDIV1 Clock 1 output divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV2 Clock 2 output divider value 24 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV3 Clock 3 output divider value 20 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV4 Clock 4 output divider value 16 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 CLKDIV2 System Clock Divider Register 2 0x1048 32 read-write n 0x0 0x0 I2SDIV I2S clock divider value 20 12 read-write I2SFRAC I2S clock divider fraction 8 8 read-write USBDIV USB clock divider divisor 1 3 read-write USBFRAC USB clock divider fraction 0 1 read-write FCFG1 Flash Configuration Register 1 0x104C 32 read-only n 0x0 0x0 DEPART FlexNVM partition 8 4 read-only EESIZE EEPROM size 16 4 read-only 0010 4 KB #0010 0011 2 KB #0011 0100 1 KB #0100 0101 512 Bytes #0101 0110 256 Bytes #0110 0111 128 Bytes #0111 1000 64 Bytes #1000 1001 32 Bytes #1001 1111 0 Bytes #1111 NVMSIZE FlexNVM size 28 4 read-only 0000 0 KB of FlexNVM #0000 0111 128 KB of FlexNVM, 16 KB protection region #0111 1001 256 KB of FlexNVM, 32 KB protection region #1001 1111 256 KB of FlexNVM, 32 KB protection region #1111 PFSIZE Program flash size 24 4 read-only 0111 128 KB of program flash memory, 4 KB protection region #0111 1001 256 KB of program flash memory, 8 KB protection region #1001 1011 512 KB of program flash memory, 16 KB protection region #1011 1111 For devices with FlexNVM (SIM_FCFG2[PFLSH]=0): 256 KB of program flash, 8 KB protection region. For devices without FlexNVM (SIM_FCFG2[PFLSH]=1): 512 KB of program flash memory, 16 KB protection region #1111 FCFG2 Flash Configuration Register 2 0x1050 32 read-only n 0x0 0x0 MAXADDR0 Max address block 0 24 6 read-only MAXADDR1 Max address block 1 16 6 read-only PFLSH Program flash 23 1 read-only 0 For devices with FlexNVM: Physical flash block 1 is used as FlexNVM For devices without FlexNVM: Reserved #0 1 Physical flash block 1 is used as program flash #1 SWAPPFLSH Swap program flash 31 1 read-only 0 Swap is not active. #0 1 Swap is active. #1 SCGC1 System Clock Gating Control Register 1 0x1028 32 read-write n 0x0 0x0 OPAMP OPAMP Clock Gate Control 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TRIAMP TRIAMP Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART4 UART4 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART5 UART5 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC2 System Clock Gating Control Register 2 0x102C 32 read-write n 0x0 0x0 DAC0 DAC0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DAC1 DAC1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ENET ENET Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC3 System Clock Gating Control Register 3 0x1030 32 read-write n 0x0 0x0 ADC1 ADC1 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM2 FTM2 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RNGB RNGB Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SDHC SDHC Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SLCD Segment LCD Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI2 SPI2 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write n 0x0 0x0 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMT CMT Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 EWM EWM Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LLWU LLWU Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART0 UART0 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART1 UART1 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART2 UART2 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART3 UART3 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 USBOTG USB Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 VREF VREF Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write n 0x0 0x0 LPTIMER Low Power Timer Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 REGFILE Register File Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TSI TSI Clock Gate Control 5 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write n 0x0 0x0 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CRC CRC Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTFL Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM0 FTM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM1 FTM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2S I2S Clock Gate Control 15 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB PDB Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Clock Gate Control 29 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 USBDCD USB DCD Clock Gate Control 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write n 0x0 0x0 DMA DMA Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXBUS FlexBus Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 MPU MPU Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SDID System Device Identification Register 0x1024 32 read-only n 0x0 0x0 FAMID Kinetis family identification 4 3 read-only 000 K10 #000 001 K20 #001 010 K30 #010 011 K40 #011 100 K60 #100 101 K70 #101 110 K50 and K52 #110 111 K51 and K53 #111 PINID Pincount identification 0 4 read-only 0010 32-pin #0010 0100 48-pin #0100 0101 64-pin #0101 0110 80-pin #0110 0111 81-pin #0111 1000 100-pin #1000 1001 121-pin #1001 1010 144-pin #1010 1100 196-pin #1100 1110 256-pin #1110 REVID Device revision number 12 4 read-only SOPT1 System Options Register 1 0x0 32 read-write n 0x0 0x0 MS EzPort chip select pin state 23 1 read-only OSC32KSEL 32K oscillator clock select 19 1 read-write 0 System oscillator (OSC32KCLK) #0 1 RTC oscillator #1 RAMSIZE RAM size 12 4 read-only 0000 Undefined #0000 0001 Undefined #0001 0010 Undefined #0010 0011 Undefined #0011 0100 Undefined #0100 0101 32 KBytes #0101 0110 Undefined #0110 0111 64 KBytes #0111 1000 96 KBytes #1000 1001 128 KBytes #1001 1010 Undefined #1010 1011 Undefined #1011 1100 Undefined #1100 1101 Undefined #1101 1110 Undefined #1110 1111 Undefined #1111 USBREGEN USB voltage regulator enable 31 1 read-write 0 USB voltage regulator is disabled. #0 1 USB voltage regulator is enabled. #1 USBSTBY USB voltage regulator in standby mode 30 1 read-write 0 USB voltage regulator not in standby. #0 1 USB voltage regulator in standby. #1 SOPT2 System Options Register 2 0x1004 32 read-write n 0x0 0x0 CMTUARTPAD CMT/UART pad drive strength 11 1 read-write 0 Single-pad drive strength for CMT IRO or UART0_TXD. #0 1 Dual-pad drive strength for CMT IRO or UART0_TXD. #1 FBSL FlexBus security level 8 2 read-write 00 All off-chip accesses (instruction and data) via the FlexBus are disallowed. #00 01 All off-chip accesses (instruction and data) via the FlexBus are disallowed. #01 10 Off-chip instruction accesses are disallowed. Data accesses are allowed. #10 11 Off-chip instruction accesses and data accesses are allowed. #11 I2SSRC I2S master clock source select 24 2 read-write 00 Core/system clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions. #00 01 MCGPLLCLK/MCGFLLCLK clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions. #01 10 OSCERCLK clock #10 11 External bypass clock (I2S0_CLKIN) #11 MCGCLKSEL MCG clock select 0 1 read-write 0 System oscillator (OSCCLK) #0 1 32 kHz RTC oscillator #1 PLLFLLSEL PLL/FLL clock select 16 1 read-write 0 MCGFLLCLK clock #0 1 MCGPLLCLK clock #1 SDHCSRC SDHC clock source select 28 2 read-write 00 Core/system clock. #00 01 MCGPLLCLK/MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 External bypass clock (SDHC0_CLKIN) #11 TIMESRC IEEE 1588 timestamp clock source select 20 2 read-write 00 Core/system clock. #00 01 MCGPLLCLK/MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 External bypass clock (ENET_1588_CLKIN). #11 TRACECLKSEL Debug trace clock select 12 1 read-write 0 MCGOUTCLK #0 1 Core/system clock #1 USBSRC USB clock source select 18 1 read-write 0 External bypass clock (USB_CLKIN). #0 1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the SIM_CLKDIV2[USBFRAC, USBDIV] descriptions. #1 SOPT4 System Options Register 4 0x100C 32 read-write n 0x0 0x0 FTM0CLKSEL FlexTimer 0 External Clock Pin Select 24 1 read-write 0 FTM_CLK0 pin #0 1 FTM_CLK1 pin #1 FTM0FLT0 FTM0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 pin #0 1 CMP0 out #1 FTM0FLT1 FTM0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 pin #0 1 CMP1 out #1 FTM0FLT2 FTM0 Fault 2 Select 2 1 read-write 0 FTM0_FLT2 pin #0 1 CMP2 out #1 FTM1CH0SRC FTM1 channel 0 input capture source select 18 2 read-write 00 FTM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM1CLKSEL FTM1 External Clock Pin Select 25 1 read-write 0 FTM_CLK0 pin #0 1 FTM_CLK1 pin #1 FTM1FLT0 FTM1 Fault 0 Select 4 1 read-write 0 FTM1_FLT0 pin #0 1 CMP0 out #1 FTM2CH0SRC FTM2 channel 0 input capture source select 20 2 read-write 00 FTM2_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM2CLKSEL FlexTimer 2 External Clock Pin Select 26 1 read-write 0 FTM2 external clock driven by FTM_CLK0 pin. #0 1 FTM2 external clock driven by FTM_CLK1 pin. #1 FTM2FLT0 FTM2 Fault 0 Select 8 1 read-write 0 FTM2_FLT0 pin #0 1 CMP0 out #1 SOPT5 System Options Register 5 0x1010 32 read-write n 0x0 0x0 UART0RXSRC UART 0 receive data source select 2 2 read-write 00 UART0_RX pin #00 01 CMP0 #01 10 CMP1 #10 UART0TXSRC UART 0 transmit data source select 0 2 read-write 00 UART0_TX pin #00 01 UART0_TX pin modulated with FTM1 channel 0 output #01 10 UART0_TX pin modulated with FTM2 channel 0 output #10 UART1RXSRC UART 1 receive data source select 6 2 read-write 00 UART1_RX pin #00 01 CMP0 #01 10 CMP1 #10 UARTTXSRC UART 1 transmit data source select 4 2 read-write 00 UART1_TX pin #00 01 UART1_TX pin modulated with FTM1 channel 0 output #01 10 UART1_TX pin modulated with FTM2 channel 0 output #10 SOPT6 System Options Register 6 0x1014 32 read-write n 0x0 0x0 RSTFLTEN Reset pin filter enable 29 3 read-write 000 All filtering disabled #000 001 Bus clock filter enabled in normal operation. LPO clock filter enabled in stop mode. #001 010 LPO clock filter enabled #010 011 Bus clock filter enabled in normal operation. All filtering disabled in stop mode. #011 100 LPO clock filter enabled in normal operation. All filtering disabled in stop mode. #100 101 Reserved (all filtering disabled) #101 110 Reserved (all filtering disabled) #110 111 Reserved (all filtering disabled) #111 RSTFLTSEL Reset pin filter select 24 5 read-write SOPT7 System Options Register 7 0x1018 32 read-write n 0x0 0x0 ADC0ALTTRGEN ADC0 alternate trigger enable 7 1 read-write 0 PDB trigger selected for ADC0. #0 1 Alternate trigger selected for ADC0. #1 ADC0PRETRGSEL ADC0 pretrigger select 4 1 read-write 0 Pre-trigger A #0 1 Pre-trigger B #1 ADC0TRGSEL ADC0 trigger select 0 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 Unused #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer trigger #1110 1111 Unused #1111 ADC1ALTTRGEN ADC1 alternate trigger enable 15 1 read-write 0 PDB trigger selected for ADC1 #0 1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. #1 ADC1PRETRGSEL ADC1 pre-trigger select 12 1 read-write 0 Pre-trigger A selected for ADC1. #0 1 Pre-trigger B selected for ADC1. #1 ADC1TRGSEL ADC1 trigger select 8 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 Unused #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer trigger #1110 1111 Unused #1111 UIDH Unique Identification Register High 0x1054 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only SPI0 Deserial Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI0 26 CTAR0 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI0 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LBS First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI0 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LBS First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE DSPI Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 5 read-write MCR DSPI Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF no description available 10 1 write-only 0 Do not clear the Rx FIFO counter. #0 1 Clear the Rx FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the Tx FIFO counter. #0 1 Clear the Tx FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF DSPI Configuration 28 2 read-write 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 Rx FIFO is enabled. #0 1 Rx FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 Tx FIFO is enabled. #0 1 Tx FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on DSPI. #0 1 Doze mode disables DSPI. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in debug mode. #0 1 Halt serial transfers in debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enable DSPI clocks. #0 1 Allow external logic to disable DSPI clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 DSPI is in slave mode. #0 1 DSPI is in master mode. #1 MTFE Modified Timing Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS[5]/PCSS is used as an active-low PCS Strobe signal. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 system clocks between SCK edge and SIN sample #00 01 1 system clock between SCK edge and SIN sample #01 10 2 system clocks between SCK edge and SIN sample #10 POPR DSPI POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR DSPI PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select. 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter. 26 1 read-write 0 Do not clear the TCR[SPI_TCNT] field. #0 1 Clear the TCR[SPI_TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS no description available 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE DSPI PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 32 read-write RSER DSPI DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE DSPI Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled #0 1 RFDF interrupt or DMA requests are enabled #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 DSPI Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 DSPI Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 DSPI Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 DSPI Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR DSPI Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 Rx FIFO is empty. #0 1 Rx FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 Tx FIFO is full. #0 1 Tx FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No Tx FIFO underflow. #0 1 Tx FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (DSPI is in stopped state). #0 1 Transmit and receive operations are enabled (DSPI is in running state). #1 TCR DSPI Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 DSPI Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 DSPI Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 DSPI Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 DSPI Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI1 Deserial Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI1 27 CTAR0 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI1 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LBS First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI1 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LBS First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE DSPI Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 5 read-write MCR DSPI Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF no description available 10 1 write-only 0 Do not clear the Rx FIFO counter. #0 1 Clear the Rx FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the Tx FIFO counter. #0 1 Clear the Tx FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF DSPI Configuration 28 2 read-write 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 Rx FIFO is enabled. #0 1 Rx FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 Tx FIFO is enabled. #0 1 Tx FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on DSPI. #0 1 Doze mode disables DSPI. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in debug mode. #0 1 Halt serial transfers in debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enable DSPI clocks. #0 1 Allow external logic to disable DSPI clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 DSPI is in slave mode. #0 1 DSPI is in master mode. #1 MTFE Modified Timing Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS[5]/PCSS is used as an active-low PCS Strobe signal. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 system clocks between SCK edge and SIN sample #00 01 1 system clock between SCK edge and SIN sample #01 10 2 system clocks between SCK edge and SIN sample #10 POPR DSPI POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR DSPI PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select. 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter. 26 1 read-write 0 Do not clear the TCR[SPI_TCNT] field. #0 1 Clear the TCR[SPI_TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS no description available 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE DSPI PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 32 read-write RSER DSPI DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE DSPI Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled #0 1 RFDF interrupt or DMA requests are enabled #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 DSPI Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 DSPI Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 DSPI Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 DSPI Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR DSPI Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 Rx FIFO is empty. #0 1 Rx FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 Tx FIFO is full. #0 1 Tx FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No Tx FIFO underflow. #0 1 Tx FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (DSPI is in stopped state). #0 1 Transmit and receive operations are enabled (DSPI is in running state). #1 TCR DSPI Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 DSPI Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 DSPI Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 DSPI Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 DSPI Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI2 Deserial Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI2 28 CTAR0 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI2 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LBS First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI2 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LBS First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE DSPI Clock and Transfer Attributes Register (In Slave Mode) SPI2 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 5 read-write MCR DSPI Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF no description available 10 1 write-only 0 Do not clear the Rx FIFO counter. #0 1 Clear the Rx FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the Tx FIFO counter. #0 1 Clear the Tx FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF DSPI Configuration 28 2 read-write 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 Rx FIFO is enabled. #0 1 Rx FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 Tx FIFO is enabled. #0 1 Tx FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on DSPI. #0 1 Doze mode disables DSPI. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in debug mode. #0 1 Halt serial transfers in debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enable DSPI clocks. #0 1 Allow external logic to disable DSPI clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 DSPI is in slave mode. #0 1 DSPI is in master mode. #1 MTFE Modified Timing Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS[5]/PCSS is used as an active-low PCS Strobe signal. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 system clocks between SCK edge and SIN sample #00 01 1 system clock between SCK edge and SIN sample #01 10 2 system clocks between SCK edge and SIN sample #10 POPR DSPI POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR DSPI PUSH TX FIFO Register In Master Mode SPI2 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select. 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter. 26 1 read-write 0 Do not clear the TCR[SPI_TCNT] field. #0 1 Clear the TCR[SPI_TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS no description available 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE DSPI PUSH TX FIFO Register In Slave Mode SPI2 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 32 read-write RSER DSPI DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE DSPI Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled #0 1 RFDF interrupt or DMA requests are enabled #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 DSPI Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 DSPI Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 DSPI Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 DSPI Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR DSPI Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 Rx FIFO is empty. #0 1 Rx FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 Tx FIFO is full. #0 1 Tx FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No Tx FIFO underflow. #0 1 Tx FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (DSPI is in stopped state). #0 1 Transmit and receive operations are enabled (DSPI is in running state). #1 TCR DSPI Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 DSPI Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 DSPI Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 DSPI Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 DSPI Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SystemControl System Control Registers SystemControl 0x0 0x8 0xD38 registers n SCB_ACTLR Auxiliary Control Register, 0x8 32 read-write n 0x0 0x0 DISDEFWBUF Disables write buffer use during default memory map accesses. 1 1 read-write DISFOLD Disables folding of IT instructions. 2 1 read-write DISMCYCINT Disables interruption of multi-cycle instructions. 0 1 read-write SCB_AFSR Auxiliary Fault Status Register 0xD3C 32 read-write n 0x0 0x0 AUXFAULT Latched version of the AUXFAULT inputs 0 32 read-write SCB_AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0x0 0x0 ENDIANNESS no description available 15 1 read-only 0 Little-endian #0 1 Big-endian #1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write SYSRESETREQ no description available 2 1 write-only 0 no system reset request #0 1 asserts a signal to the outer system that requests a reset #1 VECTCLRACTIVE no description available 1 1 write-only VECTKEY Register key 16 16 read-write VECTRESET no description available 0 1 write-only SCB_BFAR BusFault Address Register 0xD38 32 read-write n 0x0 0x0 ADDRESS Address of the BusFault location 0 32 read-write SCB_CCR Configuration and Control Register 0xD14 32 read-write n 0x0 0x0 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write 0 data bus faults caused by load and store instructions cause a lock-up #0 1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions #1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write 0 do not trap divide by 0 #0 1 trap divide by 0 #1 NONBASETHRDENA no description available 0 1 read-write 0 processor can enter Thread mode only when no exception is active #0 1 processor can enter Thread mode from any level under the control of an EXC_RETURN value #1 STKALIGN Indicates stack alignment on exception entry 9 1 read-write 0 4-byte aligned #0 1 8-byte aligned #1 UNALIGN_TRP Enables unaligned access traps 3 1 read-write 0 do not trap unaligned halfword and word accesses #0 1 trap unaligned halfword and word accesses #1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write 0 disable #0 1 enable #1 SCB_CFSR Configurable Fault Status Registers 0xD28 32 read-write n 0x0 0x0 BFARVALID no description available 15 1 read-write 0 value in BFAR is not a valid fault address #0 1 BFAR holds a valid fault address #1 DACCVIOL no description available 1 1 read-write 0 no data access violation fault #0 1 the processor attempted a load or store at a location that does not permit the operation #1 DIVBYZERO no description available 25 1 read-write 0 no divide by zero fault, or divide by zero trapping not enabled #0 1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 #1 IACCVIOL no description available 0 1 read-write 0 no instruction access violation fault #0 1 the processor attempted an instruction fetch from a location that does not permit execution #1 IBUSERR no description available 8 1 read-write 0 no instruction bus error #0 1 instruction bus error #1 IMPRECISERR no description available 10 1 read-write 0 no imprecise data bus error #0 1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error #1 INVPC no description available 18 1 read-write 0 no invalid PC load UsageFault #0 1 the processor has attempted an illegal load of EXC_RETURN to the PC #1 INVSTATE no description available 17 1 read-write 0 no invalid state UsageFault #0 1 the processor has attempted to execute an instruction that makes illegal use of the EPSR #1 LSPERR no description available 13 1 read-write 0 No bus fault occurred during floating-point lazy state preservation #0 1 A bus fault occurred during floating-point lazy state preservation #1 MLSPERR no description available 5 1 read-write 0 No MemManage fault occurred during floating-point lazy state preservation #0 1 A MemManage fault occurred during floating-point lazy state preservation #1 MMARVALID no description available 7 1 read-write 0 value in MMAR is not a valid fault address #0 1 MMAR holds a valid fault address #1 MSTKERR no description available 4 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more access violations #1 MUNSTKERR no description available 3 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more access violations #1 NOCP no description available 19 1 read-write 0 no UsageFault caused by attempting to access a coprocessor #0 1 the processor has attempted to access a coprocessor #1 PRECISERR no description available 9 1 read-write 0 no precise data bus error #0 1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault #1 STKERR no description available 12 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more BusFaults #1 UNALIGNED no description available 24 1 read-write 0 no unaligned access fault, or unaligned access trapping not enabled #0 1 the processor has made an unaligned memory access #1 UNDEFINSTR no description available 16 1 read-write 0 no undefined instruction UsageFault #0 1 the processor has attempted to execute an undefined instruction #1 UNSTKERR no description available 11 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more BusFaults #1 SCB_CPUID CPUID Base Register 0xD00 32 read-only n 0x0 0x0 IMPLEMENTER Implementer code 24 8 read-only PARTNO Indicates part number 4 12 read-only REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only SCB_DFSR Debug Fault Status Register 0xD30 32 read-write n 0x0 0x0 BKPT no description available 1 1 read-write 0 No current breakpoint debug event #0 1 At least one current breakpoint debug event #1 DWTTRAP no description available 2 1 read-write 0 No current debug events generated by the DWT #0 1 At least one current debug event generated by the DWT #1 EXTERNAL no description available 4 1 read-write 0 No EDBGRQ debug event #0 1 EDBGRQ debug event #1 HALTED no description available 0 1 read-write 0 No active halt request debug event #0 1 Halt request debug event active #1 VCATCH no description available 3 1 read-write 0 No Vector catch triggered #0 1 Vector catch triggered #1 SCB_HFSR HardFault Status register 0xD2C 32 read-write n 0x0 0x0 DEBUGEVT no description available 31 1 read-write FORCED no description available 30 1 read-write 0 no forced HardFault #0 1 forced HardFault #1 VECTTBL no description available 1 1 read-write 0 no BusFault on vector table read #0 1 BusFault on vector table read #1 SCB_ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING no description available 22 1 read-only ISRPREEMPT no description available 23 1 read-only 0 Will not service #0 1 Will service a pending exception #1 NMIPENDSET no description available 31 1 read-write 0 write: no effect; read: NMI exception is not pending #0 1 write: changes NMI exception state to pending; read: NMI exception is pending #1 PENDSTCLR no description available 25 1 write-only 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET no description available 26 1 read-write 0 write: no effect; read: SysTick exception is not pending #0 1 write: changes SysTick exception state to pending; read: SysTick exception is pending #1 PENDSVCLR no description available 27 1 write-only 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET no description available 28 1 read-write 0 write: no effect; read: PendSV exception is not pending #0 1 write: changes PendSV exception state to pending; read: PendSV exception is pending #1 RETTOBASE no description available 11 1 read-only 0 there are preempted active exceptions to execute #0 1 there are no active exceptions, or the currently-executing exception is the only active exception #1 VECTACTIVE Active exception number 0 9 read-only VECTPENDING Exception number of the highest priority pending enabled exception 12 6 read-only SCB_MMFAR MemManage Address Register 0xD34 32 read-write n 0x0 0x0 ADDRESS Address of MemManage fault location 0 32 read-write SCB_SCR System Control Register 0xD10 32 read-write n 0x0 0x0 SEVONPEND no description available 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 SLEEPDEEP no description available 2 1 read-write 0 sleep #0 1 deep sleep #1 SLEEPONEXIT no description available 1 1 read-write 0 o not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR #1 SCB_SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 BUSFAULTACT no description available 1 1 read-write 0 exception is not active #0 1 exception is active #1 BUSFAULTENA no description available 17 1 read-write 0 disable the exception #0 1 enable the exception #1 BUSFAULTPENDED no description available 14 1 read-write 0 exception is not pending #0 1 exception is pending #1 MEMFAULTACT no description available 0 1 read-write 0 exception is not active #0 1 exception is active #1 MEMFAULTENA no description available 16 1 read-write 0 disable the exception #0 1 enable the exception #1 MEMFAULTPENDED no description available 13 1 read-write 0 exception is not pending #0 1 exception is pending #1 MONITORACT no description available 8 1 read-write 0 exception is not active #0 1 exception is active #1 PENDSVACT no description available 10 1 read-write 0 exception is not active #0 1 exception is active #1 SVCALLACT no description available 7 1 read-write 0 exception is not active #0 1 exception is active #1 SVCALLPENDED no description available 15 1 read-write 0 exception is not pending #0 1 exception is pending #1 SYSTICKACT no description available 11 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTACT no description available 3 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTENA no description available 18 1 read-write 0 disable the exception #0 1 enable the exception #1 USGFAULTPENDED no description available 12 1 read-write 0 exception is not pending #0 1 exception is pending #1 SCB_SHPR1 System Handler Priority Register 1 0xD18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write SCB_SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 read-write SCB_SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write SCB_VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0x0 TBLOFF Vector table base offset 7 25 read-write SysTick System timer SysTick 0x0 0x0 0x10 registers n SYST_CALIB SysTick Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF no description available 31 1 read-only 0 The reference clock is provided #0 1 The reference clock is not provided #1 SKEW no description available 30 1 read-only 0 10ms calibration value is exact #0 1 10ms calibration value is inexact, because of the clock frequency #1 TENMS Reload value to use for 10ms timing 0 24 read-only SYST_CSR SysTick Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE no description available 2 1 read-write 0 external clock #0 1 processor clock #1 COUNTFLAG no description available 16 1 read-write ENABLE no description available 0 1 read-write 0 counter disabled #0 1 counter enabled #1 TICKINT no description available 1 1 read-write 0 counting down to 0 does not assert the SysTick exception request #0 1 counting down to 0 asserts the SysTick exception request #1 SYST_CVR SysTick Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 read-write SYST_RVR SysTick Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 read-write TRIAMP0 Trans-Impedance Amplifier TRIAMP 0x0 0x0 0x1 registers n C0 Control Register 0 0x0 8 read-write n 0x0 0x0 LPEN Low-Power Enable 6 1 read-write 0 High-speed mode selected. In this mode, TRIAMP has faster slew rate and unity gain bandwidth performance with higher current consumption. #0 1 Low-power mode selected. In this mode, TRIAMP has lower current consumption with slower slew rate and unity gain bandwidth performance. #1 TRIAMPEN TRIAMP Enable 7 1 read-write 0 The amplifier is disabled and not powered. #0 1 TRIAMP system is enabled. In this mode the amplifier is powered and enabled. #1 TRIAMP1 Trans-Impedance Amplifier TRIAMP 0x0 0x0 0x1 registers n C0 Control Register 0 0x0 8 read-write n 0x0 0x0 LPEN Low-Power Enable 6 1 read-write 0 High-speed mode selected. In this mode, TRIAMP has faster slew rate and unity gain bandwidth performance with higher current consumption. #0 1 Low-power mode selected. In this mode, TRIAMP has lower current consumption with slower slew rate and unity gain bandwidth performance. #1 TRIAMPEN TRIAMP Enable 7 1 read-write 0 The amplifier is disabled and not powered. #0 1 TRIAMP system is enabled. In this mode the amplifier is powered and enabled. #1 TSI0 Touch Sensing Input TSI0 0x0 0x0 0x160 registers n TSI0 83 CNTR1 Counter Register 0x200 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR11 Counter Register 0x73C 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR13 Counter Register 0x854 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR15 Counter Register 0x970 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR3 Counter Register 0x304 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR5 Counter Register 0x40C 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR7 Counter Register 0x518 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only CNTR9 Counter Register 0x628 32 read-only n 0x0 0x0 CTN Touch sensing channel n counter value. 16 16 read-only CTN1 Touch sensing channel n-1 counter value. 0 16 read-only GENCS General Control and Status Register 0x0 32 read-write n 0x0 0x0 EOSF End of scan flag 15 1 read-write ERIE TSI error interrupt Enable 5 1 read-write 0 Error interrupt disabled #0 1 Error interrupt enabled #1 ESOR End-of-scan or out-of-range interrupt select 4 1 read-write 0 Out-of-range interrupt selected #0 1 End-of-scan interrupt selected #1 EXTERF External electrode error occurred 13 1 read-write 0 No short #0 1 Short to VDD or VSS occured on the electrodes #1 LPCLKS Low Power Mode Clock Source Selection 28 1 read-write 0 LPOCLK #0 1 VLPOSCCLK #1 LPSCNITV TSI Low Power Mode Scan Interval 24 4 read-write 0000 1 ms scan interval #0000 0001 5 ms scan interval #0001 0010 10 ms scan interval #0010 0011 15 ms scan interval #0011 0100 20 ms scan interval #0100 0101 30 ms scan interval #0101 0110 40 ms scan interval #0110 0111 50 ms scan interval #0111 1000 75 ms scan interval #1000 1001 100 ms scan interval #1001 1010 125 ms scan interval #1010 1011 150 ms scan interval #1011 1100 200 ms scan interval #1100 1101 300 ms scan interval #1101 1110 400 ms scan interval #1110 1111 500 ms scan interval #1111 NSCN Number of Consecutive Scans per Electrode 19 5 read-write 00000 1 time per electrode #00000 00001 2 times per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 OUTRGF Out of Range Flag 14 1 read-write OVRF Overrun error flag 12 1 read-write 0 No overrun #0 1 Overrun occurred #1 PS Electrode oscillator prescaler 16 3 read-write 000 Electrode oscillator frequency divided by 1 #000 001 Electrode oscillator frequency divided by 2 #001 010 Electrode oscillator frequency divided by 4 #010 011 Electrode oscillator frequency divided by 8 #011 100 Electrode oscillator frequency divided by 16 #100 101 Electrode oscillator frequency divided by 32 #101 110 Electrode oscillator frequency divided by 64 #110 111 Electrode oscillator frequency divided by 128 #111 SCNIP Scan-in-progress status 9 1 read-only STM Scan trigger mode 1 1 read-write 0 Software trigger scan #0 1 Periodical scan #1 STPE no description available 0 1 read-write 0 Disable TSI when MCU enters low-power modes #0 1 Allow TSI to continue running in all low power modes #1 SWTS Software trigger start 8 1 write-only TSIEN TSI module enable 7 1 read-write 0 TSI disabled #0 1 TSI enabled #1 TSIIE TSI interrupt enable 6 1 read-write 0 Disable #0 1 Enable #1 PEN Pin enable register 0x8 32 read-write n 0x0 0x0 LPSP Low-power scan pin 16 4 read-write 0000 TSI_IN[0] is active in low power mode #0000 0001 TSI_IN[1] is active in low power mode #0001 0010 TSI_IN[2] is active in low power mode #0010 0011 TSI_IN[3] is active in low power mode #0011 0100 TSI_IN[4] is active in low power mode #0100 0101 TSI_IN[5] is active in low power mode #0101 0110 TSI_IN[6] is active in low power mode #0110 0111 TSI_IN[7] is active in low power mode #0111 1000 TSI_IN[8] is active in low power mode #1000 1001 TSI_IN[9] is active in low power mode #1001 1010 TSI_IN[10] is active in low power mode #1010 1011 TSI_IN[11] is active in low power mode #1011 1100 TSI_IN[12] is active in low power mode #1100 1101 TSI_IN[13] is active in low power mode #1101 1110 TSI_IN[14] is active in low power mode #1110 1111 TSI_IN[15] is active in low power mode #1111 PEN0 TSI pin 0 enable 0 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN1 TSI pin 1 enable 1 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN10 TSI pin 10 enable 10 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN11 TSI pin 11 enable 11 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN12 TSI pin 12 enable 12 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN13 TSI pin 13 enable 13 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN14 TSI pin 14 enable 14 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN15 TSI pin 15 enable 15 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN2 TSI pin 2 enable 2 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN3 TSI pin 3 enable 3 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN4 TSI pin 4 enable 4 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN5 TSI pin 5 enable 5 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN6 TSI pin 6 enable 6 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN7 TSI pin 7 enable 7 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN8 TSI pin 8 enable 8 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 PEN9 TSI pin 9 enable 9 1 read-write 0 The corresponding pin is not used by TSI #0 1 The corresponding pin is used by TSI #1 SCANC SCAN control register 0x4 32 read-write n 0x0 0x0 AMCLKDIV Active mode clock divider 5 1 read-write 0 Divider set to 1 #0 1 Divider set to 2048 #1 AMCLKS Active mode clock source 3 2 read-write 00 Bus Clock #00 01 MCGIRCLK #01 10 OSCERCLK #10 11 Not valid #11 AMPSC Active mode prescaler 0 3 read-write 000 Input clock source divided by 1 #000 001 Input clock source divided by 2 #001 010 Input clock source divided by 4 #010 011 Input clock source divided by 8 #011 100 Input clock source divided by 16 #100 101 Input clock source divided by 32 #101 110 Input clock source divided by 64 #110 111 Input clock source divided by 128 #111 CAPTRM Internal capacitance trim value 24 3 read-write 000 0.5 pF internal reference capacitance #000 001 0.6 pF internal reference capacitance #001 010 0.7 pF internal reference capacitance #010 011 0.8 pF internal reference capacitance #011 100 0.9 pF internal reference capacitance #100 101 1.0 pF internal reference capacitance #101 110 1.1 pF internal reference capacitance #110 111 1.2 pF internal reference capacitance #111 DELVOL Delta voltage select applied to analog oscillators 16 3 read-write 000 100 mV delta voltage is applied #000 001 150 mV delta voltage is applied #001 010 200 mV delta voltage is applied #010 011 250 mV delta voltage is applied #011 100 300 mV delta voltage is applied #100 101 400 mV delta voltage is applied #101 110 500 mV delta voltage is applied #110 111 600 mV delta voltage is applied #111 EXTCHRG External oscillator charge current select 19 5 read-write 00000 1 uA charge current #00000 00001 2 uA charge current #00001 00010 3 uA charge current #00010 00011 4 uA charge current #00011 00100 5 uA charge current #00100 00101 6 uA charge current #00101 00110 7 uA charge current #00110 00111 8 uA charge current #00111 01000 9 uA charge current #01000 01001 10 uA charge current #01001 01010 11 uA charge current #01010 01011 12 uA charge current #01011 01100 13 uA charge current #01100 01101 14 uA charge current #01101 01110 15 uA charge current #01110 01111 16 uA charge current #01111 10000 17 uA charge current #10000 10001 18 uA charge current #10001 10010 19 uA charge current #10010 10011 20 uA charge current #10011 10100 21 uA charge current #10100 10101 22 uA charge current #10101 10110 23 uA charge current #10110 10111 24 uA charge current #10111 11000 25 uA charge current #11000 11001 26 uA charge current #11001 11010 27 uA charge current #11010 11011 28 uA charge current #11011 11100 29 uA charge current #11100 11101 30 uA charge current #11101 11110 31 uA charge current #11110 11111 32 uA charge current #11111 REFCHRG Reference oscillator charge current select 27 5 read-write 00000 1 uA charge current #00000 00001 2 uA charge current #00001 00010 3 uA charge current #00010 00011 4 uA charge current #00011 00100 5 uA charge current #00100 00101 6 uA charge current #00101 00110 7 uA charge current #00110 00111 8 uA charge current #00111 01000 9 uA charge current #01000 01001 10 uA charge current #01001 01010 11 uA charge current #01010 01011 12 uA charge current #01011 01100 13 uA charge current #01100 01101 14 uA charge current #01101 01110 15 uA charge current #01110 01111 16 uA charge current #01111 10000 17 uA charge current #10000 10001 18 uA charge current #10001 10010 19 uA charge current #10010 10011 20 uA charge current #10011 10100 21 uA charge current #10100 10101 22 uA charge current #10101 10110 23 uA charge current #10110 10111 24 uA charge current #10111 11000 25 uA charge current #11000 11001 26 uA charge current #11001 11010 27 uA charge current #11010 11011 28 uA charge current #11011 11100 29 uA charge current #11100 11101 30 uA charge current #11101 11110 31 uA charge current #11110 11111 32 uA charge current #11111 SMOD Scan modulo 8 8 read-write 00000000 Continuous scan #00000000 STATUS Status Register 0xC 32 read-write n 0x0 0x0 ERROF0 TouchSensing Error Flag 0 16 1 read-write ERROF1 TouchSensing Error Flag 1 17 1 read-write ERROF10 TouchSensing Error Flag 10 26 1 read-write ERROF11 TouchSensing Error Flag 11 27 1 read-write ERROF12 TouchSensing Error Flag 12 28 1 read-write ERROF13 TouchSensing Error Flag 13 29 1 read-write ERROF14 TouchSensing Error Flag 14 30 1 read-write ERROF15 TouchSensing Error Flag 15 31 1 read-write ERROF2 TouchSensing Error Flag 2 18 1 read-write ERROF3 TouchSensing Error Flag 3 19 1 read-write ERROF4 TouchSensing Error Flag 4 20 1 read-write ERROF5 TouchSensing Error Flag 5 21 1 read-write ERROF6 TouchSensing Error Flag 6 22 1 read-write ERROF7 TouchSensing Error Flag 7 23 1 read-write ERROF8 TouchSensing Error Flag 8 24 1 read-write ERROF9 TouchSensing Error Flag 9 25 1 read-write ORNGF0 Touch Sensing Electrode Out-of-Range Flag 0 0 1 read-write ORNGF1 Touch Sensing Electrode Out-of-Range Flag 1 1 1 read-write ORNGF10 Touch Sensing Electrode Out-of-Range Flag 10 10 1 read-write ORNGF11 Touch Sensing Electrode Out-of-Range Flag 11 11 1 read-write ORNGF12 Touch Sensing Electrode Out-of-Range Flag 12 12 1 read-write ORNGF13 Touch Sensing Electrode Out-of-Range Flag 13 13 1 read-write ORNGF14 Touch Sensing Electrode Out-of-Range Flag 14 14 1 read-write ORNGF15 Touch Sensing Electrode Out-of-Range Flag 15 15 1 read-write ORNGF2 Touch Sensing Electrode Out-of-Range Flag 2 2 1 read-write ORNGF3 Touch Sensing Electrode Out-of-Range Flag 3 3 1 read-write ORNGF4 Touch Sensing Electrode Out-of-Range Flag 4 4 1 read-write ORNGF5 Touch Sensing Electrode Out-of-Range Flag 5 5 1 read-write ORNGF6 Touch Sensing Electrode Out-of-Range Flag 6 6 1 read-write ORNGF7 Touch Sensing Electrode Out-of-Range Flag 7 7 1 read-write ORNGF8 Touch Sensing Electrode Out-of-Range Flag 8 8 1 read-write ORNGF9 Touch Sensing Electrode Out-of-Range Flag 9 9 1 read-write THRESHLD0 Channel n threshold register 0x240 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD1 Channel n threshold register 0x364 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD10 Channel n threshold register 0xE5C 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD11 Channel n threshold register 0xFA8 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD12 Channel n threshold register 0x10F8 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD13 Channel n threshold register 0x124C 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD14 Channel n threshold register 0x13A4 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD15 Channel n threshold register 0x1500 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD2 Channel n threshold register 0x48C 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD3 Channel n threshold register 0x5B8 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD4 Channel n threshold register 0x6E8 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD5 Channel n threshold register 0x81C 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD6 Channel n threshold register 0x954 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD7 Channel n threshold register 0xA90 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD8 Channel n threshold register 0xBD0 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write THRESHLD9 Channel n threshold register 0xD14 32 read-write n 0x0 0x0 HTHH High threshold value 0 16 read-write LTHH Low threshold value 16 16 read-write UART0 Serial Communication Interface UART 0x0 0x0 0x20 registers n UART0_RX_TX 45 UART0_ERR 46 BDH UART Baud Rate Registers:High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled (use polling). #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode and receiver input is internally connected to transmitter output. #0 1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in wait mode. #0 1 UART clock freezes while CPU is in wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service. #0 1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 C7816 UART 7816 Control Register 0x18 8 read-write n 0x0 0x0 ANACK Generate NACK on Error 3 1 read-write 0 No NACK is automatically generated. #0 1 A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. #1 INIT Detect Initial Character 2 1 read-write 0 Normal operating mode. Receiver does not seek to identify initial character. #0 1 Receiver searches for initial character. #1 ISO_7816E ISO-7816 Functionality Enabled 0 1 read-write 0 ISO-7816 functionality is turned off / not enabled. #0 1 ISO-7816 functionality is turned on / enabled. #1 ONACK Generate NACK on Overflow 4 1 read-write 0 The received data does not generate a NACK when the receipt of the data results in an overflow event. #0 1 If the receiver buffer overflows, a NACK is automatically sent on a received character. #1 TTYPE Transfer Type 1 1 read-write 0 T = 0 Per the ISO-7816 specification. #0 1 T = 1 Per the ISO-7816 specification. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 ET7816 UART 7816 Error Threshold Register 0x1E 8 read-write n 0x0 0x0 RXTHRESHOLD Receive NACK Threshold 0 4 read-write TXTHRESHOLD Transmit NACK Threshold 4 4 read-write IE7816 UART 7816 Interrupt Enable Register 0x19 8 read-write n 0x0 0x0 BWTE Block Wait Timer Interrupt Enable 5 1 read-write 0 The assertion of the IS7816[BWT] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[BWT] bit will result in the generation of an interrupt. #1 CWTE Character Wait Timer Interrupt Enable 6 1 read-write 0 The assertion of the IS7816[CWT] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[CWT] bit will result in the generation of an interrupt. #1 GTVE Guard Timer Violated Interrupt Enable 2 1 read-write 0 The assertion of the IS7816[GTV] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[GTV] bit will result in the generation of an interrupt. #1 INITDE Initial Character Detected Interrupt Enable 4 1 read-write 0 The assertion of the IS7816[INITD] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[INITD] bit will result in the generation of an interrupt. #1 RXTE Receive Threshold Exceeded Interrupt Enable 0 1 read-write 0 The assertion of the IS7816[RXT] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[RXT] bit will result in the generation of an interrupt. #1 TXTE Transmit Threshold Exceeded Interrupt Enable 1 1 read-write 0 The assertion of the IS7816[TXT] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[TXT] bit will result in the generation of an interrupt. #1 WTE Wait Timer Interrupt Enable 7 1 read-write 0 The assertion of the IS7816[WT] bit will not result in the generation of an interrupt. #0 1 The assertion of the IS7816[WT] bit will result in the generation of an interrupt. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IS7816 UART 7816 Interrupt Status Register 0x1A 8 read-write n 0x0 0x0 BWT Block Wait Timer Interrupt 5 1 read-write 0 Block wait time (BWT) has not been violated. #0 1 Block wait tTime (BWT) has been violated. #1 CWT Character Wait Timer Interrupt 6 1 read-write 0 Character wait time (CWT) has not been violated. #0 1 Character wait time (CWT) has been violated. #1 GTV Guard Timer Violated Interrupt 2 1 read-write 0 A guard time (GT, CGT or BGT) has not been violated. #0 1 A guard time (GT, CGT or BGT) has been violated. #1 INITD Initial Character Detected Interrupt 4 1 read-write 0 A valid initial character has not been received. #0 1 A valid initial character has been received. #1 RXT Receive Threshold Exceeded Interrupt 0 1 read-write 0 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD]. #0 1 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. #1 TXT Transmit Threshold Exceeded Interrupt 1 1 read-write 0 The number of retries and corresponding NACKS does not exceed the value in the ET7816[TXTHRESHOLD] field. #0 1 The number of retries and corresponding NACKS exceeds the value in the ET7816[TXTHRESHOLD] field. #1 WT Wait Timer Interrupt 7 1 read-write 0 Wait time (WT) has not been violated. #0 1 Wait time (WT) has been violated. #1 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer Depth = 1 Dataword. #000 001 Receive FIFO/Buffer Depth = 4 Datawords. #001 010 Receive FIFO/Buffer Depth = 8 Datawords. #010 011 Receive FIFO/Buffer Depth = 16 Datawords. #011 100 Receive FIFO/Buffer Depth = 32 Datawords. #100 101 Receive FIFO/Buffer Depth = 64 Datawords. #101 110 Receive FIFO/Buffer Depth = 128 Datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer Depth = 1 Dataword. #000 001 Transmit FIFO/Buffer Depth = 4 Datawords. #001 010 Transmit FIFO/Buffer Depth = 8 Datawords. #010 011 Transmit FIFO/Buffer Depth = 16 Datawords. #011 100 Transmit FIFO/Buffer Depth = 32 Datawords. #100 101 Transmit FIFO/Buffer Depth = 64 Datawords. #101 110 Transmit FIFO/Buffer Depth = 128 Datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1). #0 1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 The S1[IDLE] bit is not set upon detection of an idle character. #0 1 The S1[IDLE] bit is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TL7816 UART 7816 Transmit Length Register 0x1F 8 read-write n 0x0 0x0 TLEN Transmit Length 0 8 read-write TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write WF7816 UART 7816 Wait FD Register 0x1D 8 read-write n 0x0 0x0 GTFD FD Multiplier 0 8 read-write WN7816 UART 7816 Wait N Register 0x1C 8 read-write n 0x0 0x0 GTN Guard Band N 0 8 read-write WP7816T0 UART 7816 Wait Parameter Register UART0 0x1B 8 read-write n 0x0 0x0 WI Wait Timer Interrupt (C7816[TTYPE] = 0) 0 8 read-write WP7816T1 UART 7816 Wait Parameter Register UART0 0x1B 8 read-write n 0x0 0x0 BWI Block Wait Time Integer(C7816[TTYPE] = 1) 0 4 read-write CWI Character Wait Time Integer (C7816[TTYPE] = 1) 4 4 read-write UART1 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART1_RX_TX 47 UART1_ERR 48 BDH UART Baud Rate Registers:High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled (use polling). #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode and receiver input is internally connected to transmitter output. #0 1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in wait mode. #0 1 UART clock freezes while CPU is in wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service. #0 1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer Depth = 1 Dataword. #000 001 Receive FIFO/Buffer Depth = 4 Datawords. #001 010 Receive FIFO/Buffer Depth = 8 Datawords. #010 011 Receive FIFO/Buffer Depth = 16 Datawords. #011 100 Receive FIFO/Buffer Depth = 32 Datawords. #100 101 Receive FIFO/Buffer Depth = 64 Datawords. #101 110 Receive FIFO/Buffer Depth = 128 Datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer Depth = 1 Dataword. #000 001 Transmit FIFO/Buffer Depth = 4 Datawords. #001 010 Transmit FIFO/Buffer Depth = 8 Datawords. #010 011 Transmit FIFO/Buffer Depth = 16 Datawords. #011 100 Transmit FIFO/Buffer Depth = 32 Datawords. #100 101 Transmit FIFO/Buffer Depth = 64 Datawords. #101 110 Transmit FIFO/Buffer Depth = 128 Datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1). #0 1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 The S1[IDLE] bit is not set upon detection of an idle character. #0 1 The S1[IDLE] bit is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART2 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART2_RX_TX 49 UART2_ERR 50 BDH UART Baud Rate Registers:High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled (use polling). #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode and receiver input is internally connected to transmitter output. #0 1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in wait mode. #0 1 UART clock freezes while CPU is in wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service. #0 1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer Depth = 1 Dataword. #000 001 Receive FIFO/Buffer Depth = 4 Datawords. #001 010 Receive FIFO/Buffer Depth = 8 Datawords. #010 011 Receive FIFO/Buffer Depth = 16 Datawords. #011 100 Receive FIFO/Buffer Depth = 32 Datawords. #100 101 Receive FIFO/Buffer Depth = 64 Datawords. #101 110 Receive FIFO/Buffer Depth = 128 Datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer Depth = 1 Dataword. #000 001 Transmit FIFO/Buffer Depth = 4 Datawords. #001 010 Transmit FIFO/Buffer Depth = 8 Datawords. #010 011 Transmit FIFO/Buffer Depth = 16 Datawords. #011 100 Transmit FIFO/Buffer Depth = 32 Datawords. #100 101 Transmit FIFO/Buffer Depth = 64 Datawords. #101 110 Transmit FIFO/Buffer Depth = 128 Datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1). #0 1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 The S1[IDLE] bit is not set upon detection of an idle character. #0 1 The S1[IDLE] bit is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART3 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART3_RX_TX 51 UART3_ERR 52 BDH UART Baud Rate Registers:High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled (use polling). #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode and receiver input is internally connected to transmitter output. #0 1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in wait mode. #0 1 UART clock freezes while CPU is in wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service. #0 1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer Depth = 1 Dataword. #000 001 Receive FIFO/Buffer Depth = 4 Datawords. #001 010 Receive FIFO/Buffer Depth = 8 Datawords. #010 011 Receive FIFO/Buffer Depth = 16 Datawords. #011 100 Receive FIFO/Buffer Depth = 32 Datawords. #100 101 Receive FIFO/Buffer Depth = 64 Datawords. #101 110 Receive FIFO/Buffer Depth = 128 Datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer Depth = 1 Dataword. #000 001 Transmit FIFO/Buffer Depth = 4 Datawords. #001 010 Transmit FIFO/Buffer Depth = 8 Datawords. #010 011 Transmit FIFO/Buffer Depth = 16 Datawords. #011 100 Transmit FIFO/Buffer Depth = 32 Datawords. #100 101 Transmit FIFO/Buffer Depth = 64 Datawords. #101 110 Transmit FIFO/Buffer Depth = 128 Datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1). #0 1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 The S1[IDLE] bit is not set upon detection of an idle character. #0 1 The S1[IDLE] bit is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART4 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART4_RX_TX 53 UART4_ERR 54 BDH UART Baud Rate Registers:High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled (use polling). #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode and receiver input is internally connected to transmitter output. #0 1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in wait mode. #0 1 UART clock freezes while CPU is in wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service. #0 1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer Depth = 1 Dataword. #000 001 Receive FIFO/Buffer Depth = 4 Datawords. #001 010 Receive FIFO/Buffer Depth = 8 Datawords. #010 011 Receive FIFO/Buffer Depth = 16 Datawords. #011 100 Receive FIFO/Buffer Depth = 32 Datawords. #100 101 Receive FIFO/Buffer Depth = 64 Datawords. #101 110 Receive FIFO/Buffer Depth = 128 Datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer Depth = 1 Dataword. #000 001 Transmit FIFO/Buffer Depth = 4 Datawords. #001 010 Transmit FIFO/Buffer Depth = 8 Datawords. #010 011 Transmit FIFO/Buffer Depth = 16 Datawords. #011 100 Transmit FIFO/Buffer Depth = 32 Datawords. #100 101 Transmit FIFO/Buffer Depth = 64 Datawords. #101 110 Transmit FIFO/Buffer Depth = 128 Datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1). #0 1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 The S1[IDLE] bit is not set upon detection of an idle character. #0 1 The S1[IDLE] bit is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART5 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART5_RX_TX 55 UART5_ERR 56 BDH UART Baud Rate Registers:High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled (use polling). #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by the RSRC bit. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode and receiver input is internally connected to transmitter output. #0 1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in wait mode. #0 1 UART clock freezes while CPU is in wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle-line wakeup. #0 1 Address-mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single-wire mode. #0 1 TXD pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to request interrupt service. #0 1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer(FIFO) and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer Depth = 1 Dataword. #000 001 Receive FIFO/Buffer Depth = 4 Datawords. #001 010 Receive FIFO/Buffer Depth = 8 Datawords. #010 011 Receive FIFO/Buffer Depth = 16 Datawords. #011 100 Receive FIFO/Buffer Depth = 32 Datawords. #100 101 Receive FIFO/Buffer Depth = 64 Datawords. #101 110 Receive FIFO/Buffer Depth = 128 Datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer Depth = 1 Dataword. #000 001 Transmit FIFO/Buffer Depth = 4 Datawords. #001 010 Transmit FIFO/Buffer Depth = 8 Datawords. #010 011 Transmit FIFO/Buffer Depth = 16 Datawords. #011 100 Transmit FIFO/Buffer Depth = 32 Datawords. #100 101 Transmit FIFO/Buffer Depth = 64 Datawords. #101 110 Transmit FIFO/Buffer Depth = 128 Datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or 12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1). #0 1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active (RxD input not idle). #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 The S1[IDLE] bit is not set upon detection of an idle character. #0 1 The S1[IDLE] bit is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write USB0 Universal Serial Bus, OTG Capable Controller USB0 0x0 0x0 0x10D registers n USB0 73 ADDINFO Peripheral Additional Info Register 0xC 8 read-only n 0x0 0x0 IEHOST no description available 0 1 read-only IRQNUM Assigned Interrupt Request Number 3 5 read-only ADDR Address Register 0x98 8 read-write n 0x0 0x0 ADDR USB address 0 7 read-write LSEN Low Speed Enable bit 7 1 read-write BDTPAGE1 BDT Page Register 1 0x9C 8 read-write n 0x0 0x0 BDTBA no description available 1 7 read-write BDTPAGE2 BDT Page Register 2 0xB0 8 read-write n 0x0 0x0 BDTBA no description available 0 8 read-write BDTPAGE3 BDT Page Register 3 0xB4 8 read-write n 0x0 0x0 BDTBA no description available 0 8 read-write CONTROL USB OTG Control Register 0x108 8 read-write n 0x0 0x0 DPPULLUPNONOTG no description available 4 1 read-write 0 DP Pull up in non-OTG device mode is not enabled. #0 1 DP Pull up in non-OTG device mode is enabled. #1 CTL Control Register 0x94 8 read-write n 0x0 0x0 HOSTMODEEN no description available 3 1 read-write JSTATE Live USB differential receiver JSTATE signal 7 1 read-write ODDRST no description available 1 1 read-write RESET no description available 4 1 read-write RESUME no description available 2 1 read-write SE0 Live USB Single Ended Zero signal 6 1 read-write TXSUSPENDTOKENBUSY no description available 5 1 read-write USBENSOFEN USB Enable 0 1 read-write 0 The USB Module is disabled. #0 1 The USB Module is enabled. #1 ENDPT0 Endpoint Control Register 0x180 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT1 Endpoint Control Register 0x244 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT10 Endpoint Control Register 0x9DC 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT11 Endpoint Control Register 0xAC8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT12 Endpoint Control Register 0xBB8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT13 Endpoint Control Register 0xCAC 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT14 Endpoint Control Register 0xDA4 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT15 Endpoint Control Register 0xEA0 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT2 Endpoint Control Register 0x30C 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT3 Endpoint Control Register 0x3D8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT4 Endpoint Control Register 0x4A8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT5 Endpoint Control Register 0x57C 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT6 Endpoint Control Register 0x654 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT7 Endpoint Control Register 0x730 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT8 Endpoint Control Register 0x810 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ENDPT9 Endpoint Control Register 0x8F4 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RETRYDIS no description available 6 1 read-write ERREN Error Interrupt Enable Register 0x8C 8 read-write n 0x0 0x0 BTOERREN BTOERR Interrupt Enable 4 1 read-write 0 The BTOERR interrupt is not enabled. #0 1 The BTOERR interrupt is enabled. #1 BTSERREN BTSERR Interrupt Enable 7 1 read-write 0 The BTSERR interrupt is not enabled. #0 1 The BTSERR interrupt is enabled. #1 CRC16EN CRC16 Interrupt Enable 2 1 read-write 0 The CRC16 interrupt is not enabled. #0 1 The CRC16 interrupt is enabled. #1 CRC5EOFEN CRC5/EOF Interrupt Enable 1 1 read-write 0 The CRC5/EOF interrupt is not enabled. #0 1 The CRC5/EOF interrupt is enabled. #1 DFN8EN DFN8 Interrupt Enable 3 1 read-write 0 The DFN8 interrupt is not enabled. #0 1 The DFN8 interrupt is enabled. #1 DMAERREN DMAERR Interrupt Enable 5 1 read-write 0 The DMAERR interrupt is not enabled. #0 1 The DMAERR interrupt is enabled. #1 PIDERREN PIDERR Interrupt Enable 0 1 read-write 0 The PIDERR interrupt is not enabled. #0 1 The PIDERR interrupt is enabled. #1 ERRSTAT Error Interrupt Status Register 0x88 8 read-write n 0x0 0x0 BTOERR no description available 4 1 read-write BTSERR no description available 7 1 read-write CRC16 no description available 2 1 read-write CRC5EOF no description available 1 1 read-write DFN8 no description available 3 1 read-write DMAERR no description available 5 1 read-write PIDERR no description available 0 1 read-write FRMNUMH Frame Number Register High 0xA4 8 read-write n 0x0 0x0 FRM no description available 0 3 read-write FRMNUML Frame Number Register Low 0xA0 8 read-write n 0x0 0x0 FRM no description available 0 8 read-write IDCOMP Peripheral ID Complement Register 0x4 8 read-only n 0x0 0x0 NID no description available 0 6 read-only INTEN Interrupt Enable Register 0x84 8 read-write n 0x0 0x0 ATTACHEN ATTACH Interrupt Enable 6 1 read-write 0 The ATTACH interrupt is not enabled. #0 1 The ATTACH interrupt is enabled. #1 ERROREN ERROR Interrupt Enable 1 1 read-write 0 The ERROR interrupt is not enabled. #0 1 The ERROR interrupt is enabled. #1 RESUMEEN RESUME Interrupt Enable 5 1 read-write 0 The RESUME interrupt is not enabled. #0 1 The RESUME interrupt is enabled. #1 SLEEPEN SLEEP Interrupt Enable 4 1 read-write 0 The SLEEP interrupt is not enabled. #0 1 The SLEEP interrupt is enabled. #1 SOFTOKEN SOFTOK Interrupt Enable 2 1 read-write 0 The SOFTOK interrupt is not enabled. #0 1 The SOFTOK interrupt is enabled. #1 STALLEN STALL Interrupt Enable 7 1 read-write 0 The STALL interrupt is not enabled. #0 1 The STALL interrupt is enabled. #1 TOKDNEEN TOKDNE Interrupt Enable 3 1 read-write 0 The TOKDNE interrupt is not enabled. #0 1 The TOKDNE interrupt is enabled. #1 USBRSTEN USBRST Interrupt Enable 0 1 read-write 0 The USBRST interrupt is not enabled. #0 1 The USBRST interrupt is enabled. #1 ISTAT Interrupt Status Register 0x80 8 read-write n 0x0 0x0 ATTACH Attach Interrupt 6 1 read-write ERROR no description available 1 1 read-write RESUME no description available 5 1 read-write SLEEP no description available 4 1 read-write SOFTOK no description available 2 1 read-write STALL Stall Interrupt 7 1 read-write TOKDNE no description available 3 1 read-write USBRST no description available 0 1 read-write OBSERVE USB OTG Observe Register 0x104 8 read-only n 0x0 0x0 DMPD no description available 4 1 read-only 0 D- pulldown disabled. #0 1 D- pulldown enabled. #1 DPPD no description available 6 1 read-only 0 D+ pulldown disabled. #0 1 D+ pulldown enabled. #1 DPPU no description available 7 1 read-only 0 D+ pullup disabled. #0 1 D+ pullup enabled. #1 OTGCTL OTG Control Register 0x1C 8 read-write n 0x0 0x0 DMLOW D- Data Line pull-down resistor enable 4 1 read-write 0 D- pulldown resistor is not enabled. #0 1 D- pulldown resistor is enabled. #1 DPHIGH D+ Data Line pullup resistor enable 7 1 read-write 0 D+ pullup resistor is not enabled #0 1 D+ pullup resistor is enabled #1 DPLOW D+ Data Line pull-down resistor enable 5 1 read-write 0 D+ pulldown resistor is not enabled. #0 1 D+ pulldown resistor is enabled. #1 OTGEN On-The-Go pullup/pulldown resistor enable 2 1 read-write 0 If USB_EN is set and HOST_MODE is clear in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is set the D+ and D- Data Line pull-down resistors are engaged. #0 1 The pull-up and pull-down controls in this register are used. #1 OTGICR OTG Interrupt Control Register 0x14 8 read-write n 0x0 0x0 AVBUSEN A VBUS Valid interrupt enable 0 1 read-write 0 The AVBUSCHG interrupt is disabled #0 1 The AVBUSCHG interrupt is enabled #1 BSESSEN B Session END interrupt enable 2 1 read-write 0 The B_SESS_CHG interrupt is disabled #0 1 The B_SESS_CHG interrupt is enabled #1 IDEN ID interrupt enable 7 1 read-write 0 The ID interrupt is disabled #0 1 The ID interrupt is enabled #1 LINESTATEEN Line State change interrupt enable 5 1 read-write 0 The LINE_STAT_CHG interrupt is disabled. #0 1 The LINE_STAT_CHG interrupt is enabled #1 ONEMSECEN 1 millisecond interrupt enable 6 1 read-write 0 The 1msec timer interrupt is disabled. #0 1 The 1msec timer interrupt is enabled. #1 SESSVLDEN Session valid interrupt enable 3 1 read-write 0 The SESSVLDCHG interrupt is disabled. #0 1 The SESSVLDCHG interrupt is enabled. #1 OTGISTAT OTG Interrupt Status Register 0x10 8 read-write n 0x0 0x0 AVBUSCHG no description available 0 1 read-write B_SESS_CHG no description available 2 1 read-write IDCHG no description available 7 1 read-write LINE_STATE_CHG no description available 5 1 read-write ONEMSEC no description available 6 1 read-write SESSVLDCHG no description available 3 1 read-write OTGSTAT OTG Status Register 0x18 8 read-write n 0x0 0x0 AVBUSVLD A VBUS Valid 0 1 read-write 0 The VBUS voltage is below the A VBUS Valid threshold. #0 1 The VBUS voltage is above the A VBUS Valid threshold. #1 BSESSEND B Session END 2 1 read-write 0 The VBUS voltage is above the B session End threshold. #0 1 The VBUS voltage is below the B session End threshold. #1 ID no description available 7 1 read-write 0 Indicates a Type A cable has been plugged into the USB connector #0 1 Indicates no cable is attached or a Type B cable has been plugged into the USB connector #1 LINESTATESTABLE no description available 5 1 read-write 0 The LINE_STAT_CHG bit is not yet stable. #0 1 The LINE_STAT_CHG bit has been debounced and is stable. #1 ONEMSECEN no description available 6 1 read-write SESS_VLD Session valid 3 1 read-write 0 The VBUS voltage is below the B session Valid threshold #0 1 The VBUS voltage is above the B session Valid threshold. #1 PERID Peripheral ID Register 0x0 8 read-only n 0x0 0x0 ID Peripheral identification bits 0 6 read-only REV Peripheral Revision Register 0x8 8 read-only n 0x0 0x0 REV Revision 0 8 read-only SOFTHLD SOF Threshold Register 0xAC 8 read-write n 0x0 0x0 CNT no description available 0 8 read-write STAT Status Register 0x90 8 read-only n 0x0 0x0 ENDP no description available 4 4 read-only ODD no description available 2 1 read-only TX Transmit Indicator 3 1 read-only 0 The most recent transaction was a Receive operation. #0 1 The most recent transaction was a Transmit operation. #1 TOKEN Token Register 0xA8 8 read-write n 0x0 0x0 TOKENENDPT no description available 0 4 read-write TOKENPID no description available 4 4 read-write 0001 OUT Token. USB Module performs an OUT (TX) transaction. #0001 1001 IN Token. USB Module performs an In (RX) transaction. #1001 1101 SETUP Token. USB Module performs a SETUP (TX) transaction #1101 USBCTRL USB Control Register 0x100 8 read-write n 0x0 0x0 PDE no description available 6 1 read-write 0 Weak pulldowns are disabled on D+ and D- #0 1 Weak pulldowns are enabled on D+ and D-. #1 SUSP no description available 7 1 read-write 0 USB transceiver is not in suspend state. #0 1 USB transceiver is in suspend state. #1 USBTRC0 USB Transceiver Control Register 0 0x10C 8 read-write n 0x0 0x0 SYNC_DET Synchronous USB Interrupt Detect 1 1 read-only 0 Synchronous interrupt has not been detected. #0 1 Synchronous interrupt has been detected. #1 USBRESET USB reset 7 1 write-only 0 Normal USB module operation. #0 1 Returns the USB module to its reset state. #1 USBRESMEN Asynchronous Resume Interrupt Enable 5 1 read-write 0 USB asynchronous wakeup from suspend mode disabled. #0 1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interupt should only be enabled when the Transceiver is suspended. #1 USB_RESUME_INT USB Asynchronous Interrupt 0 1 read-only 0 No interrupt was generated. #0 1 Interrupt was generated because of the USB asynchronous interrupt. #1 USBDCD USB Device Charger Detection module USBDCD 0x0 0x0 0x1C registers n USBDCD 74 CLOCK Clock Register 0x4 32 read-write n 0x0 0x0 CLOCK_SPEED Numerical Value of Clock Speed in Binary 2 10 read-write CLOCK_UNIT Unit of measurement encoding for Clock Speed 0 1 read-write 0 kHz Speed (between 1 kHz and 1023 kHz) #0 1 MHz Speed (between 1 MHz and 1023 MHz) #1 CONTROL Control Register 0x0 32 read-write n 0x0 0x0 IACK Interrupt Acknowledge 0 1 write-only 0 Do not clear the interrupt. #0 1 Clear the IF bit (interrupt flag). #1 IE Interrupt Enable 16 1 read-write 0 Disable interrupts to the system. #0 1 Enable interrupts to the system. #1 IF Interrupt Flag 8 1 read-only 0 No interrupt is pending. #0 1 An interrupt is pending. #1 SR Software Reset 25 1 write-only 0 Do not perform a software reset. #0 1 Perform a software reset. #1 START Start Change Detection Sequence 24 1 write-only 0 Do not start the sequence. Writes of this value have no effect. #0 1 Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. #1 STATUS Status Register 0x8 32 read-only n 0x0 0x0 ACTIVE Active Status Indicator 22 1 read-only 0 The sequence is not running. #0 1 The sequence is running. #1 ERR Error Flag 20 1 read-only 0 No sequence errors. #0 1 Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. #1 SEQ_RES Charger Detection Sequence Results 16 2 read-only 00 No results to report. #00 01 Attached to a standard host. Must comply with USB Spec 2.0 by drawing only 2.5mA (max) until connected. #01 10 Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a charging host or a dedicated charger (The charger type detection has not completed.) 1: Attached to a charging host (The charger type detection has completed.) #10 11 Attached to a dedicated charger. #11 SEQ_STAT Charger Detection Sequence Status 18 2 read-only 00 The module is either not enabled, or the module is enabled but the data pins have not yet been detected. #00 01 Data pin contact detection is complete. #01 10 Charger detection is complete. #10 11 Charger type detection is complete. #11 TO Timeout Flag 21 1 read-only 0 The detection sequence has not been running for over 1 s. #0 1 It has been over 1 s since the data pin contact was detected and debounced.{ #1 TIMER0 TIMER0 Register 0x10 32 read-write n 0x0 0x0 TSEQ_INIT Sequence Initiation Time 16 10 read-write TUNITCON Unit Connection Timer Elapse (in ms) 0 12 read-only TIMER1 no description available 0x14 32 read-write n 0x0 0x0 TDCD_DBNC Time Period to Debounce D+ Signal 16 10 read-write TVDPSRC_ON Time Period Comparator Enabled 0 10 read-write TIMER2 no description available 0x18 32 read-write n 0x0 0x0 CHECK_DM Time Before Check of D- Line 0 4 read-write TVDPSRC_CON Time Period Before Enabling D+ Pullup 16 10 read-write VREF Voltage Reference VREF 0x0 0x0 0x2 registers n SC VREF Status and Control Register 0x1 8 read-write n 0x0 0x0 MODE_LV Buffer Mode selection 0 2 read-write 00 Bandgap on only, for stabilization and startup #00 10 Tight-regulation buffer enabled #10 REGEN Regulator enable 6 1 read-write 0 Internal 1.75 V regulator is disabled. #0 1 Internal 1.75 V regulator is enabled. #1 VREFEN Internal Voltage Reference enable 7 1 read-write 0 The module is disabled. #0 1 The module is enabled. #1 VREFST Internal Voltage Reference has settled 2 1 read-only 0 The bandgap is disabled or not ready. #0 1 The bandgap is ready. #1 TRM VREF Trim Register 0x0 8 read-write n 0x0 0x0 TRIM Trim bits 0 6 read-write 000000 Min #000000 111111 Max #111111 WDOG Generation 2008 Watchdog Timer WDOG 0x0 0x0 0x18 registers n Watchdog 22 PRESC Watchdog Prescaler Register 0x16 16 read-write n 0x0 0x0 PRESCVAL no description available 8 3 read-write REFRESH Watchdog Refresh Register 0xC 16 read-write n 0x0 0x0 WDOGREFRESH no description available 0 16 read-write RSTCNT Watchdog Reset Count Register 0x14 16 read-write n 0x0 0x0 RSTCNT no description available 0 16 read-write STCTRLH Watchdog Status and Control Register High 0x0 16 read-write n 0x0 0x0 ALLOWUPDATE no description available 4 1 read-write 0 No further updates allowed to WDOG write once registers. #0 1 WDOG write once registers can be unlocked for updating. #1 BYTESEL no description available 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 CLKSRC no description available 1 1 read-write 0 Dedicated clock source selected as WDOG clock (LPO Oscillator). #0 1 WDOG clock sourced from alternate clock source. #1 DBGEN no description available 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 DISTESTWDOG no description available 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 IRQRSTEN no description available 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT time, it generates a reset. #1 STNDBYEN no description available 8 1 read-write 0 WDOG is disabled in system Standby mode. #0 1 WDOG is enabled in system Standby mode. #1 STOPEN no description available 6 1 read-write 0 WDOG is disabled in CPU stop mode. #0 1 WDOG is enabled in CPU stop mode. #1 TESTSEL no description available 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 TESTWDOG no description available 10 1 read-write WAITEN no description available 7 1 read-write 0 WDOG is disabled in CPU wait mode. #0 1 WDOG is enabled in CPU wait mode. #1 WDOGEN no description available 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 WINEN no description available 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write n 0x0 0x0 INTFLG no description available 15 1 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write n 0x0 0x0 TIMEROUTHIGH no description available 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write n 0x0 0x0 TIMEROUTLOW no description available 0 16 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write n 0x0 0x0 TOVALHIGH no description available 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write n 0x0 0x0 TOVALLOW no description available 0 16 read-write UNLOCK Watchdog Unlock Register 0xE 16 read-write n 0x0 0x0 WDOGUNLOCK no description available 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write n 0x0 0x0 WINHIGH no description available 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write n 0x0 0x0 WINLOW no description available 0 16 read-write